PCA9671 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 29 September 2011 16 of 33
NXP Semiconductors
PCA9671
Remote 16-bit I/O expander for Fm+ I
2
C-bus with reset
8.4 Power-on reset
When power is applied to V
DD
, an internal Power-On Reset (POR) holds the PCA9671 in
a reset condition until V
DD
has reached V
POR
. At that point, the reset condition is released
and the PCA9671 registers and I
2
C-bus/SMBus state machine will initialize to their default
states. Thereafter V
DD
must be lowered below 0.2 V to reset the device.
8.5 RESET input
A reset can be accomplished by holding the RESET pin LOW for a minimum of t
w(rst)
. The
PCA9671 registers and I
2
C-bus state machine will be held in their default state until the
RESET
input is once again HIGH.
9. Characteristics of the I
2
C-bus
The I
2
C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
9.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 17
).
9.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 18
).
Fig 17. Bit transfer
mba607
data line
stable;
data valid
change
of data
allowed
SDA
SCL
