OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

6-102203-1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33
PCA9671 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 29 September 2011 19 of 33
NXP Semiconductors
PCA9671
Remote 16-bit I/O expander for Fm+ I
2
C-bus with reset
10.2 High current-drive load applications
The GPIO has a maximum sinking current of 25 mA per bit. In applications requiring
additional drive, two port pins in the same octal may be connected together to sink up to
50 mA current. Both bits must then always be turned on or off together. Up to 8 pins (one
octal) can be connected together to drive 200 mA.
11. Limiting values
[1] Total package (maximum) output current is 600 mA.
Fig 22. High current-drive load application
002aac254
V
DD
P00
P01
P02
P03
P04
P05
P06
P07
V
DD
SDA
SCL
RESET
A0
A1
A2
CORE
PROCESSOR
V
DD
LOAD
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DD
supply voltage 0.5 +6 V
I
DD
supply current - 100 mA
I
SS
ground supply current - 600 mA
V
I
input voltage V
SS
0.5 5.5 V
I
I
input current - 20 mA
I
O
output current - 50
[1]
mA
P
tot
total power dissipation - 600 mW
P/out power dissipation per output - 200 mW
T
stg
storage temperature 65 +150 C
T
amb
ambient temperature operating 40 +85 C
PCA9671 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 29 September 2011 20 of 33
NXP Semiconductors
PCA9671
Remote 16-bit I/O expander for Fm+ I
2
C-bus with reset
12. Static characteristics
[1] The power-on reset circuit resets the I
2
C-bus logic with V
DD
<V
POR
and set all I/Os to logic 1 (with current source to V
DD
).
[2] Each bit must be limited to a maximum of 25 mA and the total package limited to 400 mA due to internal busing limits.
[3] The value is not tested, but verified on sampling basis.
Table 5. Static characteristics
V
DD
= 2.3 V to 5.5 V; V
SS
=0V; T
amb
=
40
Cto+85
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Supplies
V
DD
supply voltage 2.3 - 5.5 V
I
DD
supply current operating mode; no load;
V
I
=V
DD
or V
SS
; f
SCL
= 400 kHz
- 200 500 A
I
stb
standby current standby mode; no load;
V
I
=V
DD
or V
SS
-2.510A
V
POR
power-on reset voltage
[1]
-1.82.0V
Input SCL; input/output SDA
V
IL
LOW-level input voltage 0.5 - +0.3V
DD
V
V
IH
HIGH-level input voltage 0.7V
DD
-5.5V
I
OL
LOW-level output current V
OL
=0.4V 20--mA
I
L
leakage current V
I
=V
DD
or V
SS
1- +1A
C
i
input capacitance V
I
=V
SS
-410pF
I/Os; P00 to P07 and P10 to P17
I
OL
LOW-level output current V
OL
=0.5V; V
DD
=2.3V
[2]
12 27 - mA
V
OL
=0.5V; V
DD
=3.0V
[2]
17 35 - mA
V
OL
=0.5V; V
DD
=4.5V
[2]
25 42 - mA
I
OL(tot)
total LOW-level output current V
OL
=0.5V; V
DD
=4.5V
[2]
--400mA
I
OH
HIGH-level output current V
OH
=V
SS
30 150 300 A
I
trt(pu)
transient boosted pull-up current V
OH
=V
SS
; see Figure 14 0.5 1.0 - mA
C
i
input capacitance
[3]
-410pF
C
o
output capacitance
[3]
-410pF
Input RESET
V
IL
LOW-level input voltage 0.5 - +0.8 V
V
IH
HIGH-level input voltage 2 - 5.5 V
I
LI
input leakage current 1- +1A
C
i
input capacitance - 3 5 pF
Inputs AD0, AD1, AD2
V
IL
LOW-level input voltage 0.5 - +0.3V
DD
V
V
IH
HIGH-level input voltage 0.7V
DD
-5.5V
I
LI
input leakage current 1- +1A
C
i
input capacitance - 3 5 pF
PCA9671 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 29 September 2011 21 of 33
NXP Semiconductors
PCA9671
Remote 16-bit I/O expander for Fm+ I
2
C-bus with reset
13. Dynamic characteristics
[1] t
VD;ACK
= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
[2] t
VD;DAT
= minimum time for SDA data out to be valid following SCL LOW.
[3] C
b
= total capacitance of one bus line in pF.
[4] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V
IL
of the SCL signal) in order to
bridge the undefined region SCL’s falling edge.
Table 6. Dynamic characteristics
V
DD
= 2.3 V to 5.5 V; V
SS
=0V; T
amb
=
40
Cto+85
C; unless otherwise specified.
Symbol Parameter Conditions Standard-mode
I
2
C-bus
Fast-mode I
2
C-bus Fast-mode
Plus I
2
C-bus
Unit
Min Max Min Max Min Max
f
SCL
SCL clock frequency 0 100 0 400 0 1000 kHz
t
BUF
bus free time between a
STOP and START
condition
4.7 - 1.3 - 0.5 - s
t
HD;STA
hold time (repeated)
START condition
4.0 - 0.6 - 0.26 - s
t
SU;STA
set-up time for a repeated
START condition
4.7 - 0.6 - 0.26 - s
t
SU;STO
set-up time for STOP
condition
4.0 - 0.6 - 0.26 - s
t
HD;DAT
data hold time 0 - 0 - 0 - ns
t
VD;ACK
data valid acknowledge
time
[1]
0.3 3.45 0.1 0.9 0.05 0.45 s
t
VD;DAT
data valid time
[2]
300 - 50 - 50 450 ns
t
SU;DAT
data set-up time 250 - 100 - 50 - ns
t
LOW
LOW period of the SCL
clock
4.7 - 1.3 - 0.5 - s
t
HIGH
HIGH period of the SCL
clock
4.0 - 0.6 - 0.26 - s
t
f
fall time of both SDA and
SCL signals
[4][5]
- 300 20 + 0.1C
b
[3]
300 - 120 ns
t
r
rise time of both SDA and
SCL signals
- 1000 20 + 0.1C
b
[3]
300 - 120 ns
t
SP
pulse width of spikes that
must be suppressed by
the input filter
[6]
-50 - 50-50ns
Port timing; C
L
100 pF (see Figure 15 and Figure 14)
t
v(Q)
data output valid time - 4 - 4 - 4 s
t
su(D)
data input set-up time 0 - 0 - 0 - s
t
h(D)
data input hold time 4 - 4 - 4 - s
Reset timing (see Figure 24
)
t
w(rst)
reset pulse width 4 - 4 - 4 - ns
t
rec(rst)
reset recovery time 0 - 0 - 0 - ns
t
rst
reset time 100 - 100 - 100 - ns
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33

6-102203-1

Mfr. #:
Buy 6-102203-1
Manufacturer:
TE Connectivity / AMP Connectors
Description:
Headers & Wire Housings SHROUDED RA SNGL 14 with standoffs
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet