QT1103-ISG Datasheet QT1103-ISG | P4-P6

1.2.10 Adjacent Key Suppression (AKS™)

AKS™ is a Quantum-patented feature that can be enabled

via a resistor strap option. AKS works to prevent multiple

keys from responding to a single touch, a common complaint

about capacitive touch panels. This can happen with closely

spaced keys, or with control surfaces that have water films on

them.

AKS operates by comparing signal strengths from keys within

a group of keys to suppress touch detections from those that

have a weaker signal change than the dominant one.

The QT1103 has two different AKS groupings of keys,

selectable via option resistors. These groupings are:

• AKS operates in three groups of keys

• AKS operates over all ten keys

These two modes allow the designer to provide AKS while

also providing for shift or function operations.

If AKS is disabled, all keys can operate simultaneously.

1.2.11 Outputs

The QT1103 has a serial output using one or two wires,

RS-232 data format, and automatic baud rate detection. A

simple protocol is employed.

The QT1103 operates in slave mode, i.e. it only sends data

to the host after receiving a request from the host.

An additional /CHANGE (state changed) signal allows the

use of the serial interface to be optimised, rather than being

polled continuously.

1.2.12 Simplified Mode

To reduce the need for option resistors, the simplified

operating mode places the part into fixed settings with only

the AKS feature being selectable. LP mode is also possible

in this configuration. Simplified mode is suitable for most

applications.

4 QT1103_3R0.03_0607

1.3 Wiring

VddInput for 2W mode2W ReceiveIRX32

-Requires pull-up to Vdd1W mode serial I/OI/OD1W31

100k resistor to Vss

0 = a key state has changed

Requires pull-up

State changedOD/CHANGE30

Open---n/c29

OpenTo Cs9 + KeySense pinI/OSNS9K28

OpenTo Cs9Sense pinI/OSNS927

OpenTo Cs8 + KeySense pinI/OSNS8K26

OpenTo Cs8Sense pinI/OSNS825

OpenSee Table 1.4Detect StatusO/ODDETECT24

Vdd or Vss**Rising edge sync or LP pulseSync In or LP InISYNC/LP

‡

-0VGroundPVss22

OpenTo Cs7 + KeySense pinI/OSNS7K21

Open or mode resistor

†

or option

resistor*

To Cs7 and/or mode resistor

†

or option resistor*

Sense pin and mode

or option select

I/OSNS720

Open or

mode resistor

†

To Cs6 + Key and/or

mode resistor

†

Sense pin and

mode select

I/OSNS6K19

Open or

option resistor*

To Cs6 and/or

option resistor*

Sense pin and

option select

I/OSNS618

OpenTo Cs5 + KeySense pinI/OSNS5K17

Open or

option resistor*

To Cs5 and/or

option resistor *

Sense pin and

option select

I/OSNS516

OpenTo Cs4 + KeySense pinI/OSNS4K15

OpenTo Cs4Sense pinI/OSNS414

OpenTo Cs3 + KeySense pinI/OSNS3K13

Open or

option resistor*

To Cs3 and/or

option resistor*

Sense pin and

option select

I/OSNS312

OpenTo Cs2 + KeySense pinI/OSNS2K11

Open or

option resistor*

To Cs2 and/or

option resistor*

Sense pin and

option select

I/OSNS210

OpenTo Cs1 + KeySense pinI/OSNS1K9

Open or

option resistor*

To Cs1 and/or

option resistor*

Sense pin and

option select

I/OSNS18

OpenTo Cs0 + KeySense pinI/OSNS0K7

Open or

option resistor*

To Cs0 and/or

option resistor

Sense pin and

option select

I/OSNS06

-Leave open--n/c5

Resistor to Vdd and optional

spread spectrum RC network

OscillatorIOSC4

-+2.8 ~ +5.0VPowerPVdd3

-Active low resetReset inputI/RST2

100k resistor to Vss

Spread spectrum driveSpread spectrumODSS1

If UnusedNotesFunctionTypeNamePin

Table 1.1 Pin Descriptions

Pin Type

I CMOS input only

I/O CMOS I/O

OD CMOS open drain output

I/OD CMOS input or open drain output

O/OD CMOS push-pull or open-drain output (option selected)

P Ground or power

Notes

†

Mode resistor is required only in Simplified mode (see Figure 1.2)

* Option resistor is required only in Full Options mode (see Figure 1.1)

‡

Pin is either Sync or LP depending on options selected (functions SL_0, SL_1, see Figure 1.1)

** See text

5 QT1103_3R0.03_0607

Table 1.2

AKS / Fast-Detect Options

Table 1.3

Max On-Duration

Table 1.4

Detect Pin Drive

Table 1.5

SYNC/LP Function

6 QT1103_3R0.03_0607

Figure 1.1 Connection Diagram - Full Options (32-QFN Package)

VDD

*100nF

VSS

DETECT

SYNC/LP

DETECT OUT

SYNC or LP

Pull-up not required for push-pull mode

See Detect pin mode table

100K

Vdd

QT1103

32-QFN

100K

/CHANGE

N.C.

/CHANGE

DATA

2W DATA

Vdd

100K

Vdd

100K

Vdd

N.C.

OSC

Rb1

Rb2

Css

VDD

With Spread-Spectrum

No Spread-Spectrum

Vdd Range Rb1 Rb2

2.8 ~ 2.99V 12K 27K

3.0 ~ 3.59V 12K 22K

3.6 ~ 5V 15K 27K

2.8 ~ 2.99V 15K dni

3.0 ~ 3.59V 18K dni

3.6 ~ 5V 20K dni

dni = do not install

Recommended Rb1, Rb2 Value

*Note: One bypass capacitor to be tightly wired between

Vdd and Vss. Follow regulator manufacturer’s

recommendations for input and output capacitors.

SNS6

SNS6K

SNS7

SNS7K

KEY 6

KEY 7

Keep these parts

close to the IC

V / V

DD SS

SL_0

SNS6

V / V

DD SS

SL_1

SNS7

SNS4

SNS4K

SNS5

SNS5K

KEY 4

KEY 5

SNS4

V / V

DD SS

SNS5

OUT_D

SNS3

SNS3K

KEY 3

V / V

DD SS

MOD_1

SNS3

SNS8

SNS8K

SNS9

SNS9K

KEY 8

KEY 9

SNS8

SNS9

SNS2K

SNS2

KEY 2

DD SS

MOD_0

SNS2

SNS1K

SNS1

KEY 1

SNS0K

SNS0

KEY 0

Keep these parts

close to the IC

SNS1

SNS0

DD SS

AKS_1

DD SS

AKS_0

Vunreg

Voltage Reg

VDD

/RST

RESET IN

OffOn, globalVddVdd

OffOn, in 3 groupsVssVdd

EnabledOffVddVss

OffOffVssVss

FAST-DETECTAKS MODEAKS_0AKS_1

(reserved)VddVdd

Infinite (disabled)VssVdd

60 seconds to recalibrateVddVss

10 seconds to recalibrateVssVss

MAX ON-DURATION MODEMOD_0MOD_1

Push-pull, active highVdd

Open drain, active lowVss

DETECT PIN MODEOUT_D

LP mode: 190ms response timeVddVdd

LP mode: 110ms response timeVssVdd

LP mode: 70ms response timeVddVss

SyncVssVss

SYNC/LP PIN MODESL_0SL_1

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P22

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