NCP4304A, NCP4304B
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13
APPLICATION INFORMATION
General Description
The NCP4304A/B is designed to operate either as
a standalone IC or as a companion IC to a primary side
controller to help achieve efficient synchronous
rectification in switch mode power supplies. This controller
features a high current gate driver along with high-speed
logic circuitry to provide appropriately timed drive signals
to a synchronous rectification MOSFET. With its novel
architecture, the NCP4304A/B has enough versatility to
keep the synchronous rectification efficient under any
operating mode.
The NCP4304A/B works from an available bias supply
with voltage range from 10.4 V to 28 V (typical). The wide
V
CC
range allows direct connection to the SMPS output
voltage of most adapters such as notebook and LCD TV
adapters. As a result, the NCP4304A/B simplifies circuit
operation compared to other devices that require specific
bias power supplies (e.g. 5 V). The high voltage capability
of the V
CC
is also a unique feature designed to allow
operation for a broader range of applications.
Precise turn off threshold of the current sense comparator
together with accurate offset current source allows the user
to adjust for any required turn off current threshold of the SR
MOSFET switch using a single resistor. Compared to other
SR controllers that provide turn off thresholds in the range
of −10 mV to −5 mV, the NCP4304A/B offers a turn off
threshold of 0 mV that in combination with a low R
DS(on)
SR
MOSFET significantly reduces the turn off current
threshold and improves efficiency.
To overcome issues after turn on and off events, the
NCP4304A/B provides adjustable minimum on time and off
time blanking periods. Blanking times can be adjusted
independently of IC V
CC
using resistors connected to GND.
If needed, blanking periods can be modulated using
additional components.
An ultrafast trigger input helps to implement synchronous
rectification systems in CCM applications (like CCM
flyback or forward). The time delay from trigger input to
driver turn off event is 10 ns (typicaly). Additionally, the
trigger input can be used to disable the IC and activate a low
consumption standby mode. This feature can be used to
decrease standby consumption of an SMPS.
Finally, the NCP4304A/B features a special input that can
be used to automatically compensate for SR MOSFET
parasitic inductance effect. This technique achieves the
maximum available on-time and thus optimizes efficiency
when a MOSFET in standard package (like TO−220 or
TO247) is used. If a SR MOSFET in SMT package with
negligible inductance is used, the compensation input is
connected to GND pin.
Zero Current Detection and Parasitic Inductance
Compensation
Figure 40 shows the internal connection of the ZCD
circuitry on the current sense input. The synchronous
rectification MOSFET is depicted with it’s parasitic
inductances to demonstrate operation of the compensation
system.
Figure 40. ZCD Sensing Circuitry Functionality
+
+
SR MOSFET
LDRAIN LSOURCE
M1
RSHIFT_CS
I
shift_CS
+
+Vout
GND
DRV
CS
COMP GND
Vdd
ZCD SET
ZCD RESET
To Internal Logic
V
th_cs_off
+
+
V
REF
= V
th_cs_on
I
shift_CS
100 mA
−1
LCOMP
NCP4304A, NCP4304B
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14
When the voltage on the secondary winding of the SMPS
reverses, the body diode of M1 starts to conduct current and
the voltage of M1’s drain drops approximately to −1 V. The
CS pin sources current of 100 mA that creates a voltage drop
on the RSHIFT_CS resistor. Once the voltage on the CS pin
is lower than V
th_cs_on
threshold, M1 is turned on. Because
of parasitic impedances, significant ringing can occur in the
application. To overcome sudden turn-off due to mentioned
ringing, the minimum conduction time of the SR MOSFET
is activated. Minimum conduction time can be adjusted
using R
MIN_TON
resistor.
The SR MOSFET is turned-off as soon as the voltage on
the CS pin is higher than V
th_cs_off
. For the same ringing
reason, a minimum off time timer is asserted once the
turnoff is detected. The minimum off time can be externally
adjusted using R
MIN_TOFF
resistor. MOSFET M1 conducts
when the secondary current decreases, therefore the turn-off
time depends on its R
DS(on)
. The 0 mV threshold provides
an optimum switching period usage while keeping enough
time margin for the gate turn off. The RSHIFT_CS resistor
provides the designer with the possibility to modify
(increase) the actual turn-off current threshold.
V
DS
Figure 41. ZCD Comparators Thresholds and Blanking Periods Timing
I
SEC
V
DRV
Blank
V
th_cs_off
− (RSHIFT_CS I
shift_CS
)
V
th_cs_on
− (RSHIFT_CS I
shift_CS
)
t
on_min
t
off_min
The t
on_min
and t
off_min
are adjustable by R
MIN_TON
and R
MIN_TOFF
resistors.
If no RSHIFT_CS resistor is used, the turn-on and turn-off
thresholds are fully given by the CS input specification
(please refer to parametric table). Once non-zero
RSHIFT_CS resistor is used, both thresholds move down
(i.e. higher MOSFET turn off current) as the CS pin offset
current causes a voltage drop that is equal to:
V
RSHIFT_CS
+ RSHIFT_CS @ I
shift_CS
(eq. 1)
Final turn-on and turn-off thresholds can be then calculated
as:
V
CS_turn_on
+ V
th_cs_on
*
ǒ
RSHIFT_CS @ I
shift_CS
Ǔ
(eq. 2)
V
CS_turn_off
+ V
th_cs_off
*
ǒ
RSHIFT_CS @ I
shift_CS
Ǔ
(eq. 3)
Note that RSHIFT_CS impact on turn-on threshold is less
critical compare to turn-off threshold.
If using a SR MOSFET in TO−220 package (or other
package which features leads), the parasitic inductance of
the package leads causes a turn-off current threshold
increase. This is because current that flows through the SR
MOSFET has quite high di(t)/dt that induces error voltage
on the SR MOSFET leads inductance. This error voltage,
that is proportional to the secondary current derivative,
shifts the CS input voltage to zero when significant current
still flows through the channel. Zero current threshold is thus
detected when current still flows through the SR MOSFET
channel – please refer to Figure 42 for better understanding.
As a result, the SR MOSFET is turned-off prematurely and
the efficiency of the SMPS is not optimized.
NCP4304A, NCP4304B
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15
Figure 42. Waveforms from SR System Using MOSFET in TO−220 Package Without Parasitic Inductance
Compensation – SR MOSFET Channel Conduction Time is Reduced
Note that the efficiency impact of the error caused by
parasitic inductance increases with lower R
DS(on)
MOSFETs and/or higher operating frequency.
The NCP4304A/B offers a way to compensate for
MOSFET parasitic inductances effect − refer to Figure 43.
Figure 43. Package Parasitic Inductances Compensation Principle
D
CS
S
GND COMP
LCOMPLSOURCER
DS(on)
LDRAIN
V
LCOMP
V
LSOURCE
V
RDS(on)
V
LDRAIN
V
DS
I
SEC
Dedicated input (COMP) offers the possibility to use an
external compensation inductance (wire strap or PCB). If
the value of this compensation inductance is LCOMP =
LDRAIN + LSOURCE, the compensation voltage created
on this inductance is exactly the same as the sum of error
voltages created on drain and source parasitic inductances
i.e. V
LDRAIN
+V
LSOURCE
. The internal analog inverter
(Figure 40) inverts compensation voltage V
LCOMP
and
offsets the current sense comparator turn-off threshold. The
current sense comparator thus “sees” between its terminals
a voltage that would be seen on the SR MOSFET channel
resistance in case the lead inductances wouldn’t exist. The
current sense comparator of the NCP4304A/B is thus able to
detect the secondary current zero crossing very precisely.
More over, the secondary current turn-off threshold is then
di(t)/t independent thus the NCP4304A/B allows to increase
operating frequency of the SR system. One should note that
the parasitic resistance of compensation inductance should

NCP4304ADR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Switching Controllers SEC SIDE SYNC RECT DRV
Lifecycle:
New from this manufacturer.
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