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16
be as low as possible compared to the SR MOSFET channel
and leads resistance otherwise compensation is not efficient.
Typical value of compensation inductance for a TO−220
package is 7 nH. Waveforms from the application with
compensated SR system can be seen in Figure 44. One can
see the conduction time has been significantly increased and
turn-off current reduced.
Figure 44. Waveforms SR System Using MOSFET in TO−220 Package with Parasitic Inductance Compensation –
SR MOSFET Channel Conduction Time is Optimized
Note that using the compensation system is only
beneficial in applications that are using a low R
DS(on)
MOSFET in non-SMT package. Using the compensation
method allows for optimized efficiency with a standard
TO−220 package that in turn results in reduced costs, as the
SMT MOSFETs usually require reflow soldering process
and more expensive PCB.
From the above paragraphs and parameter tables it is
evident that turn-off threshold precision is quite critical. If
we consider a SR MOSFET with R
DS(on)
of 1 mW, the 1 mV
error voltage on the CS pin results in a 1 A turn-off current
threshold difference. Thus the PCB layout is very critical
when implementing the SR system. Note that the CS turn-off
comparator as well as compensation inputs are referred to
the GND pin. Any parasitic impedance (resistive or
inductive − talking about mW and nH values) can cause a
high error voltage that is then evaluated by the CS
comparator. Ideally the CS turn-off comparator should
detect voltage that is caused by secondary current directly on
the SR MOSFET channel resistance. Practically this is not
possible because of the bonding wires, leads and soldering.
To assure the best efficiency results, a Kelvin connection of
the SR controller to the power circuitry should be
implemented (i.e. GND pin should be connected to the SR
MOSFET source soldering point and current sense pin
should be connected to the SR MOSFET drain soldering
point). Any impact of PCB parasitic elements on the SR
controller functionality is then avoided. Figures 45 and 46
show examples of SR system layouts using parasitic
inductance compensation (i.e. for low R
DS(on)
MOSFET in
TO−220 package ) and not using compensation (i.e. for
higher R
DS(on)
MOSFET in TO−220 package or SMT
package MOSFETs).
