NCP4304A, NCP4304B
www.onsemi.com
19
Advantage of the trigger blanking time during DRV
turn-ON event is evident from Figure 50. Rising edge of the
DRV signal may cause additional spikes on the TRIG/DIS
input. These spikes, in combination with ultra-fast
performance of the trigger logic, could turn-OFF the SR
MOSFET in inappropriate time. Implementation of the
trigger blanking time period helps to avoid such situation.
Figure 50. Trigger Blanking Masked-out Noise in Trigger Signal During Switch-ON Event
t0
t3
DRV
TRIG/DIS
V
DS
V
th_cs_off
V
th_cs_on
Min_ON_Time
Disable of Trigger
120 ns
t1
t2
t4 t5 t6
Figure 51 depicts driver turn-OFF events in details. If the
CS (V
DS
) stays below V
th_cs_off
threshold driver is
turned-OFF according to rising edge of the TRIG/DIS
signal. TRIG/DIS can turn-OFF the driver also during
minimum-ON time period (time marker t2 and t3 in
Figure 51).
Figure 52 depicts another driver turn-OFF events in
details. Driver is turned-OFF according to the CS (V
DS
)
signal (t2 marker) and only after minimum-ON time
elapsed. TRIG/DIS signal needs to be LOW during this
event. If the CS (V
DS
) voltage reaches V
th_cs_off
threshold
before minimum-ON time period ends and TRIG/DIS pin is
LOW the DRV is turned-OFF on the falling edge of the
minimum-ON time period (t4 and t6 time markers in
Figure 52).
Figure 53 depicts performance of the NCP4304A/B
controller when trigger pin is permanently pulled LOW. In
this case the DRV is turned ON and OFF according to the CS
(V
DS
) signal. The driver can be turned off only after
minimum-ON time period elapsed. The driver is turned-ON
in the time when CS (V
DS
) reaches V
th_cs_on
threshold
(t1−t2, t5–t6, t9–t10 markers). DRV is turned-OFF if CS
(V
DS
) signal reaches V
th_cs_off
threshold (t4 marker). The
DRV ON-time is prolonged till minimum-ON time period
falling edge if the CS (V
DS
) reaches V
th_cs_off
before
minimum-ON time period elapsed (t7−t8, t11−t12 markers).
Figure 54 depicts entering into the sleep mode. If the
TRIG/DIS is pulled up for more than 100 ms the
NCP4304A/B enters low consumption mode. The DRV
stays LOW (disabled) during entering sleep mode.
Figure 55 shows sleep mode transition 2nd case – i.e.
TRIG/DIS rising edge comes during the trigger blank
period.
Figure 56 depicts entering into sleep mode and wake-up
sequence.
Figures 57 and 58 show wake-up situations in details. If
the NCP4304A/B is in sleep mode and TRIG/DIS is pulled
LOW NCP4304A/B requires up to 10 ms period to recover
all internal circuitry to normal operation mode. The driver
is then enabled in the next cycle of CS (V
DS
) signal only.
The DRV stays LOW during waking-up time period.
