NCP4304A, NCP4304B
www.onsemi.com
22
Figure 55. TRIG/DIS from LOW to HIGH Sequence 2
Figure 56. Sleep Mode Sequence
t0 t3
DRV
Min_ON_Time
t1 t2
Power Consumption
100 ms
120 ns
t0 t3
DRV
TRIG/DIS
V
DS
t1 t2
Power
Consumption
100 ms
Sleep Mode
10 ms
t4
TRIG/DIS
V
DS
V
th_cs_off
V
th_cs_on
NCP4304A, NCP4304B
www.onsemi.com
23
Figure 57. Waking-up Sequence
Figure 58. Wake-up Time Sequence
t0 t3
DRV
Power
Consumption
t1 t2 t4 t5 t6 t7 t8
Sleep Mode
Driver
LOW
10 ms
Wake Up
DRV
t0
t3t1
t2
t4 t5
Waking-up Time Waked Up
T1
Sleep
Mode
t9
TRIG/DIS
V
DS
V
th_cs_off
V
th_cs_on
TRIG/DIS
V
DS
V
th_cs_off
V
th_cs_on
NCP4304A, NCP4304B
www.onsemi.com
24
Figure 59 shows IC behavior in case the trigger signal
features two pulses during one cycle of the V
DS
(CS) signal.
TRIG/DIS enables driver at time t1 and DRV turns ON
because the V
DS
voltage is under V
th_cs_on
threshold
voltage. The trigger signal and consequently DRV output
fall down in time t2. The minimum OFF time generator is
triggered in time t2. TRIG/DIS drops down to LOW level in
time t3 but there is still minimum OFF time sequence present
so the DRV output stays low. When the minimum OFF time
sequence elapses in time t4 the DRV is turned ON. In time
t5 Trigger signal rises up and terminates this cycle of the CS
signal in time t5. Next cycle starts in time t6. Trigger enables
DRV and V
DS
is under V
th_cs_on
threshold voltage so DRV
turns ON in time t6. TRIG/DIS signal rises up to HIGH level
in time t7, consequently DRV turns OFF and this starts
minimum OFF time generator. Because minimum OFF time
period is longer then the rest of time to the end of cycle of
V
DS
− DRV is disabled.
Figure 59. IC Behavior when Multiple Trigger Pulses Appear on TRIG/DIS Input
t0 t3
DRV
TRIG/DIS
V
DS
Min_ON_Time
t1 t2 t4 t5 t6 t7 t8
V
th_cs_off
V
th_cs_on
Min_OFF_Time
t9 t10
Note that the TRIG/DIS input is an ultrafast input that is
sensitive even to very narrow voltage pulses. Thus it is wise
to keep this input on a low impedance path and provide it
with a clean triggering signal in the time this input is enabled
by internal logic.
A typical application schematic of a CCM flyback
converter with the NCP4304A/B driver can be seen in
Figure 60. In this application the trigger signal is taken
directly from the flyback controller driver output and
transmitted to the secondary side by pulse transformer TR2.
Because the TRIG/DIS input is edge sensitive, it is not
necessary to transmit the entire primary driver pulse to the
secondary. The coupling capacitor C5 is used to allow pulse
transformer core reset and also to prepare a needle pulse
(a pulse with width lower than 100 ns) to be transmitted to
the NCP4304A/B TRIG/DIS input. The advantage of needle
trigger pulse usage is that the required volt-second product
of the pulse transformer is very low and that allows the
designer to use very small and cheap magnetics. The trigger
transformer can be for instance prepared on a small toroidal
ferrite core with diameter of 8 mm. Proper safety insulation
between primary and secondary sides can be easily assured
by using triple insulated wire for one or even both windings.
The primary MOSFET gate voltage rising edge is delayed
by external circuitry consisting of transistors Q1, Q2 and
surrounding components. The primary MOSFET is thus
turned-on with a slight delay so that the secondary controller
turns-off the SR MOSFET by trigger signal prior to the
primary switching. This method reduces the commutation
losses and the SR MOSFET drain voltage spike, which
results in improved efficiency.
It is also possible to use capacitive coupling (use
additional capacitor with safety insulation) between the
primary and secondary to transmit the trigger signal. We do
not recommend this technique as the parasitic capacitive
currents between primary and secondary may affect the
trigger signal and thus overall system functionality.

NCP4304BMNTWG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Switching Controllers SEC SIDE SYNC RECT DRV
Lifecycle:
New from this manufacturer.
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