TJA1052I All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 5 — 29 January 2018 22 of 27
NXP Semiconductors
TJA1052i
Galvanically isolated high-speed CAN transceiver
17. Appendix: ISO 11898-2:2016 parameter cross-reference list
Table 15. ISO 11898-2:2016 to NXP data sheet parameter conversion
ISO 11898-2:2016 NXP data sheet
Parameter Notation Symbol Parameter
HS-PMA dominant output characteristics
Single ended voltage on CAN_H V
CAN_H
V
O(dom)
dominant output voltage
Single ended voltage on CAN_L V
CAN_L
Differential voltage on normal bus load V
Diff
V
O(dif)
differential output voltage
Differential voltage on effective resistance during arbitration
Optional: Differential voltage on extended bus load range
HS-PMA driver symmetry
Driver symmetry V
SYM
V
TXsym
transmitter voltage symmetry
Maximum HS-PMA driver output current
Absolute current on CAN_H I
CAN_H
I
O(sc)dom
dominant short-circuit output
current
Absolute current on CAN_L I
CAN_L
HS-PMA recessive output characteristics, bus biasing active/inactive
Single ended output voltage on CAN_H V
CAN_H
V
O(rec)
recessive output voltage
Single ended output voltage on CAN_L V
CAN_L
Differential output voltage V
Diff
V
O(dif)
differential output voltage
Optional HS-PMA transmit dominant timeout
Transmit dominant timeout, long t
dom
t
to(dom)TXD
TXD dominant time-out time
Transmit dominant timeout, short
HS-PMA static receiver input characteristics, bus biasing active/inactive
Recessive state differential input voltage range
Dominant state differential input voltage range
V
Diff
V
th(RX)dif
differential receiver threshold
voltage
V
rec(RX)
receiver recessive voltage
V
dom(RX)
receiver dominant voltage
HS-PMA receiver input resistance (matching)
Differential internal resistance R
Diff
R
i(dif)
differential input resistance
Single ended internal resistance R
CAN_H
R
CAN_L
R
i
input resistance
Matching of internal resistance MR R
i
input resistance deviation
HS-PMA implementation loop delay requirement
Loop delay t
Loop
t
d(TXDH-RXDH)
delay time from TXD HIGH to
RXD HIGH
t
d(TXDL-RXDL)
delay time from TXD LOW to RXD
LOW
Optional HS-PMA implementation data signal timing requirements for use with bit rates above 1 Mbit/s up to
2 Mbit/s and above 2 Mbit/s up to 5 Mbit/s
Transmitted recessive bit width @ 2 Mbit/s / @ 5 Mbit/s,
intended
t
Bit(Bus)
t
bit(bus)
transmitted recessive bit width
Received recessive bit width @ 2 Mbit/s / @ 5 Mbit/s t
Bit(RXD)
t
bit(RXD)
bit time on pin RXD
Receiver timing symmetry @ 2 Mbit/s / @ 5 Mbit/s t
Rec
t
rec
receiver timing symmetry
