TJA1052I All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 5 — 29 January 2018 4 of 27
NXP Semiconductors
TJA1052i
Galvanically isolated high-speed CAN transceiver
6. Pinning information
6.1 Pinning
6.2 Pin description
[1] All GND1 pins (pins 2, 7 and 8) should be connected together and to ground domain 1. All GND2 pins (pins
9, 10 and 15) should be connected together and to ground domain 2. Refer to the application notes for
further information.
[2] Setting STB HIGH disables the CAN bus connection.
Fig 2. Pin configuration diagram
7-$L
9
''
9
''
*1' *1'
7;'
67%
QF
&$1+
5;' &$1/
QF 9
''
*1' *1'
*1' *1'
DDD







Table 4. Pin description
Symbol Pin Description
V
DD1
1 supply voltage 1
GND1 2 ground supply 1
[1]
TXD 3 transmit data input
n/c 4 not connected
RXD 5 receive data output; reads out data from the bus lines
n/c 6 not connected
GND1 7 ground supply 1
[1]
GND1 8 ground supply 1
[1]
GND2 9 ground supply 2
[1]
GND2 10 ground supply 2
[1]
V
DD2
11 supply voltage 2
CANL 12 LOW-level CAN bus line
CANH 13 HIGH-level CAN bus line
STB 14 Standby mode control input
[2]
GND2 15 ground supply 2
[1]
V
DD2
16 supply voltage 2
TJA1052I All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 5 — 29 January 2018 5 of 27
NXP Semiconductors
TJA1052i
Galvanically isolated high-speed CAN transceiver
7. Functional description
7.1 Operation
7.1.1 Normal mode
During normal operation, the TJA1052i transceiver transmits and receives data via bus
lines CANH and CANL (see Figure 1
for the block diagram). The differential receiver
converts the analog data on the bus lines into digital data, which is output on pin RXD.
The slopes of the output signals on the bus lines are controlled internally and are
optimized in a way that guarantees the lowest possible EME.
The isolator used in the TJA1052i is an AC device that employs on-off keying to
guarantee the DC output state at all times. The states of TXD, RXD and the CAN bus at
start-up, shut-down and during normal operation are described in Table 5
.
Care should be taken regarding power sequencing if the device is used in networks that
support remote wake-up (see Section 12 “
Application information).
7.1.2 Standby mode
The TJA1052i cannot transmit or receive regular CAN messages in Standby mode. Only
the isolator and low-power CAN receiver are active, monitoring the bus lines for activity.
The bus wake-up filter ensures that only bus dominant and bus recessive states that
persist longer than t
fltr(wake)bus
are reflected on the RXD pin (see Figure 3). To reduce
current consumption, the CAN bus is terminated to GND and not biased to V
DD2
/2 as in
Normal mode.
Standby mode is selected by setting pin STB HIGH. The TJA1052i also switches to
Standby mode when an undervoltage is detected on V
DD2
(V
uvd(swoff)(VDD2)
< V
DD2
<
V
uvd(stb)(VDD2)
; Section 7.2.3). An internal pull-up ensures that Standby mode is selected
by default when pin STB is not connected.
In Standby mode:
The CAN transmitter if off
The normal CAN receiver is off
The low-power CAN receiver is active
CANH and CANL are biased to GND
The signal received at the low-power CAN receiver is reflected on pin RXD
V
DD2
undervoltage detection is active
Table 5. Input/output states at start-up, shut-down and during normal operation
TXD RXD V
DD1
V
DD2
CAN Comments
HH>V
uvd(VDD1)
>V
uvd(stb)VDD2)
recessive Normal mode operation
LL>V
uvd(VDD1)
>V
uvd(stb)VDD2)
dominant Normal mode with TXD dominant time-out active
X X unpowered >V
uvd(stb)VDD2)
dominant dominant after V
DD1
power loss until TXD dominant
timeout; recessive while V
DD2
is ramping up from
an unpowered state
XL>V
uvd(VDD1)
unpowered disconnected RXD transitions L-to-H when V
DD2
restored
TJA1052I All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 5 — 29 January 2018 6 of 27
NXP Semiconductors
TJA1052i
Galvanically isolated high-speed CAN transceiver
The isolation function of the TJA1052i is not disabled in Standby mode. Overall quiescent
current is not reduced significantly in this mode. The TJA1052i is not designed to support
CAN bus wake-up functionality with very low quiescent currents.
7.2 Fail-safe features
7.2.1 TXD dominant time-out function
A ‘TXD dominant time-out’ timer is started when pin TXD goes LOW. If the LOW state on
TXD persists for longer than t
to(dom)TXD
, the transmitter is disabled, releasing the bus lines
to recessive state. This function prevents a hardware and/or software application failure
from driving the bus lines to a permanent dominant state (blocking all network
communications). The TXD dominant time-out timer is reset by a positive edge on TXD.
The TXD dominant time-out time also defines the minimum possible bit rate of 40 kbit/s.
7.2.2 Bus dominant time-out function
In Standby mode, a 'bus dominant time-out' timer is started when the CAN bus changes
from recessive to dominant state. If the dominant state on the bus persists for longer than
t
to(dom)bus
, the RXD pin is forced HIGH. This prevents a clamped dominant bus (due to a
bus short-circuit or a failure in one of the other nodes on the network) generating a
permanent wake-up request. The bus dominant time-out timer is reset when the CAN bus
changes from dominant to recessive state.
7.2.3 Undervoltage protection: V
DD2
If the voltage on pin V
DD2
falls below the standby threshold, V
uvd(stb)(VDD2)
, the transceiver
switches to Standby mode. The TJA1052i will remain in Standby mode until V
DD2
rises
above V
uvd(stb)(VDD2)
(max). The low-power receiver continues to monitor the bus while the
TJA1052i is in Standby mode. Data on the bus is still reflected onto RXD, but the transfer
speed is reduced.
If the voltage on V
DD2
falls below the switch-off threshold, V
uvd(swoff)(VDD2)
, the transceiver
switches off and disengages from the bus (zero load). It is guaranteed to switch on again
in Standby mode when V
DD2
rises above V
uvd(swoff)(VDD2)
(max).
Fig 3. Wake-up timing
DDD
&$1+
&$1/
9
2GLI
W
IOWUZDNHEXV
W
IOWUZDNHEXV
W
IOWUZDNHEXV
WW
IOWUZDNHEXV
W
IOWUZDNHEXV
WW
IOWUZDNHEXV
5;'

TJA1052IT/5Y

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
CAN Interface IC CAN Transceiver High Speed
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet