CBTL02042A_CBTL02042B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 1 — 10 March 2011 7 of 16
NXP Semiconductors
CBTL02042A; CBTL02042B
3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen2
12. Dynamic characteristics
[1] Typical values are at V
DD
= 3.3 V; T
amb
=25°C, and maximum loading.
Table 7. Dynamic characteristics
V
DD
=3.3V
±
10 %; T
amb
=
−
40
°
C to +85
°
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ
[1]
Max Unit
DDIL differential insertion loss channel is OFF
f=100MHz - −50 - dB
f=2.5GHz - −25 - dB
channel is ON
f=100MHz - −0.5 - dB
f=2.5GHz - −1.2 - dB
DDNEXT differential near-end crosstalk adjacent channels are ON
f=100MHz - −50 - dB
f=2.5GHz - −30 - dB
B
−3dB
−3 dB bandwidth - 7.0 - GHz
DDRL differential return loss f = 100 MHz - −25 - dB
f=2.5GHz - −20 - dB
R
on
ON-state resistance V
DD
= 3.3 V; V
I
=2V; I
I
=19mA - 6 - Ω
t
PD
propagation delay from Port A to Port B, or Port A
to Port C, or vice versa
-80-ps
Switching characteristics
t
startup
start-up time supply voltage valid or XSD
going LOW to channel specified
operating characteristics
--10ms
t
PZH
OFF-state to HIGH propagation delay - - 300 ns
t
PZL
OFF-state to LOW propagation delay - - 70 ns
t
PHZ
HIGH to OFF-state propagation delay - - 50 ns
t
PLZ
LOW to OFF-state propagation delay - - 50 ns
t
sk(dif)
differential skew time intra-pair - 5 - ps
t
sk
skew time inter-pair - - 35 ps
