89HPES16H16ZABL Datasheet 89HPES16H16ZABRI, 89HPES16H16ZABL, 89HPES16H16ZABR | P7-P9

7 of 36 October 3, 2011

IDT 89HPES16H16 Data Sheet

GPIO[14] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: P9RSTN

Alternate function pin type: Output

Alternate function: Reset output for downstream port 9

GPIO[15] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: P10RSTN

Alternate function pin type: Output

Alternate function: Reset output for downstream port 10

GPIO[16] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: P11RSTN

Alternate function pin type: Output

Alternate function: Reset output for downstream port 11

GPIO[17] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: P12RSTN

Alternate function pin type: Output

Alternate function: Reset output for downstream port 12

GPIO[18] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: P13RSTN

Alternate function pin type: Output

Alternate function: Reset output for downstream port 13

GPIO[19] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: P14RSTN

Alternate function pin type: Output

Alternate function: Reset output for downstream port 14

GPIO[20] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: P15RSTN

Alternate function pin type: Output

Alternate function: Reset output for downstream port 15

GPIO[21] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: IOEXPINTN0

Alternate function pin type: Input

Alternate function: SMBus I/O expander interrupt 0

GPIO[22]

I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: IOEXPINTN1

Alternate function pin type: Input

Alternate function: SMBus I/O expander interrupt 1

GPIO[23] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: IOEXPINTN2

Alternate function pin type: Input

Alternate function: SMBus I/O expander interrupt 2

Signal Type Name/Description

Table 4 General Purpose I/O Pins (Part 3 of 4)

8 of 36 October 3, 2011

IDT 89HPES16H16 Data Sheet

GPIO[24] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: IOEXPINTN3

Alternate function pin type: Input

Alternate function: SMBus I/O expander interrupt 3

GPIO[25]

I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: IOEXPINTN4

Alternate function pin type: Input

Alternate function: SMBus I/O expander interrupt 4

GPIO[26] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: IOEXPINTN5

Alternate function pin type: Input

Alternate function: SMBus I/O expander interrupt 5

GPIO[27] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: IOEXPINTN6

Alternate function pin type: Input

Alternate function: SMBus I/O expander interrupt 6

GPIO[28] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: IOEXPINTN7

Alternate function pin type: Input

Alternate function: SMBus I/O expander interrupt 7

GPIO[29] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

GPIO[30] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

GPIO[31] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: IOEXPINTN10

Alternate function pin type: Input

Alternate function: SMBus I/O expander interrupt 10

GPIO pins 22 and 25 are not available in the 23x23mm package.

Signal Type Name/Description

CCLKDS I Common Clock Downstream. When the CCLKDS pin is asserted, it indicates that a

common clock is being used between the downstream device and the downstream

port.

CCLKUS I Common Clock Upstream. When the CCLKUS pin is asserted, it indicates that a

common clock is being used between the upstream device and the upstream port.

MSMBSMODE I Master SMBus Slow Mode. The assertion of this pin indicates that the master SMBus

should operate at 100 KHz instead of 400 KHz. This value may not be overridden.

Table 5 System Pins (Part 1 of 2)

Signal Type Name/Description

Table 4 General Purpose I/O Pins (Part 4 of 4)

9 of 36 October 3, 2011

IDT 89HPES16H16 Data Sheet

PERSTN I Fundamental Reset. Assertion of this signal resets all logic inside the PES16H16 and

initiates a PCI Express fundamental reset.

RSTHALT I Reset Halt. When this signal is asserted during a PCI Express fundamental reset, the

PES16H16 executes the reset procedure and remains in a reset state with the Master

and Slave SMBuses active. This allows software to read and write registers internal to

the device before normal device operation begins. The device exits the reset state

when the RSTHALT bit is cleared in the PA_SWCTL register by an SMBus master.

SWMODE[3:0] I Switch Mode. These configuration pins determine the PES16H16 switch operating

mode. These pins should be static and not change following the negation of PERSTN.

0x0 - Normal switch mode

0x1 - Normal switch mode with Serial EEPROM initialization

0x2 through 0x7 - Reserved

0x8 - Normal switch mode with upstream port failover (port 0 selected as the

upstream port)

0x9 - Normal switch mode with upstream port failover (port 2 selected as the

upstream port)

0xA - Normal switch mode with Serial EEPROM initialization and upstream port

failover (port 0 selected as the upstream port)

0xB - Normal switch mode with Serial EEPROM initialization and upstream port

failover (port 2 selected as the upstream port)

0xC through 0xF - Reserved

Signal Type Name/Description

JTAG_TCK I JTAG Clock. This is an input test clock used to clock the shifting of data into or out of

the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system

clock with a nominal 50% duty cycle.

JTAG_TDI I JTAG Data Input. This is the serial data input to the boundary scan logic or JTAG

Controller.

JTAG_TDO O JTAG Data Output. This is the serial data shifted out from the boundary scan logic or

JTAG Controller. When no data is being shifted out, this signal is tri-stated.

JTAG_TMS I JTAG Mode. The value on this signal controls the test mode select of the boundary

scan logic or JTAG Controller.

JTAG_TRST_N I JTAG Reset. This active low signal asynchronously resets the boundary scan logic

and JTAG TAP Controller. An external pull-up on the board is recommended to meet

the JTAG specification in cases where the tester can access this signal. However, for

systems running in functional mode, one of the following should occur:

1) actively drive this signal low with control logic

2) statically drive this signal low with an external pull-down on the board

Table 6 Test Pins

Signal Type Name/Description

CORE I Core VDD. Power supply for core logic.

I/O I I/O VDD. LVTTL I/O buffer power supply.

PE I PCI Express Digital Power. PCI Express digital power used by the digital power of

the SerDes.

Table 7 Power and Ground Pins

Signal Type Name/Description

Table 5 System Pins (Part 2 of 2)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36

89HPES16H16ZABL

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Description:

PCI Interface IC PCIE 16-LANE 16 PORT SWITCH

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