PDF: 09005aef817ab1fc/Source: 09005aef817ab1dd Micron Technology, Inc., reserves the right to change products or specifications without notice.
HTF9C32_64_128x72K.fm - Rev. C 9/06 EN
13 ©2005 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB: (x72, SR) 244-Pin DDR2 Registered MiniDIMM
Register and PLL Specifications
PLL
Notes: 1. PLL timing and switching specifications are critical for proper operation of the DDR2 DIMM.
This is a subset of parameters for the specific PLL used. Detailed PLL information is available
in JEDEC Standard JESD82.
2. The output slew rate is determined from the IBIS model:
Table 14: PLL (CU877 device or Equivilent JESD82-8.01)
Parameter Symbol Pins Condition Min Max Units
DC high-level input voltage
V
IH RESET# LVCMOS 0.65 × VDD –mV
DC low-level input voltage
V
IL RESET# LVCMOS 0.35 × VDD mV
Input voltage (limits)
V
IN RESET#, CK, CK# –0.3 VDDQ + 0.3 mV
DC high-level input voltage
V
IH CK, CK# Differential input 0.65 × VDD –mV
DC low-level input voltage
V
IL CK, CK# Differential input 0.35 × VDD mV
Input differential-pair cross
voltage
V
IX CK, CK# Differential input (VDDQ/2) -
0.15
(VDDQ/2) +
0.15
V
Input differential voltage
V
ID(DC) CK, CK# Differential input 0.3 VDDQ + 0.4 V
Input differential voltage
V
ID(AC) CK, CK# Differential input 0.6 VDDQ + 0.4 V
Input current
I
I RESET# VI = VDDQ or VSSQ –10 10 µA
CK, CK# V
I = VDDQ or VSSQ –250 250 µA
Output disabled current
I
ODL RESET# = VSSQ; VI = VIH(AC) or
VIL(DC)
100 µA
Static supply current
I
DDLD CK = CK# = LOW 500 µA
Dynamic supply
I
DD N/A CK, CK# = 270 MHz, all
outputs open
(not connected to PCB)
–300mA
Input capacitance
C
IN Each input VI = VDDQ or VSSQ23pF
Table 15: PLL Clock Driver Timing Requirements and Switching Characteristics
Note: 1
Parameter Symbol
0°C T
OPR
+55°C
VDD = +1.8V ±0.1V
UnitsMin Max
Stabilization time
t
L–15µs
Input clock slew rate
t
LS
I
1.0 4 V/ns
SSC modulation frequency
30 33 KHz
SSC clock input frequency deviation
0.0 –0.50 %
PLL loop bandwidth (-3dB from unity gain)
2.0 MHz
VDD
GND
V
DD
CU877
R = 60Ω
R = 60Ω
VCK
VCK
2
PDF: 09005aef817ab1fc/Source: 09005aef817ab1dd Micron Technology, Inc., reserves the right to change products or specifications without notice.
HTF9C32_64_128x72K.fm - Rev. C 9/06 EN
14 ©2005 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB: (x72, SR) 244-Pin DDR2 Registered MiniDIMM
Register and PLL Specifications
Notes: 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and
the falling or rising edge of SDA.
2. This parameter is sampled.
3. For a restart condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
t
WRC) is the time from a valid stop condition of a write
sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE
cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resis-
tor, and the EEPROM does not respond to its slave address.
Table 16: Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to VSS; VDDSPD = +1.7V to +3.6V
Parameter/Condition Symbol Min Max Units
Supply voltage
V
DDSPD 1.7 3.6 V
Input high voltage: Logic 1; All inputs
V
IH VDDSPD × 0.7 VDDSPD + 0.5 V
Input low voltage: Logic 0; All inputs
V
IL –0.6 VDDSPD × 0.3 V
Output low voltage: I
OUT = 3mA
V
OL –0.4V
Input leakage current: V
IN = GND to VDDSPD
ILI 0.10 3 µA
Output leakage current: V
OUT = GND to VDDSPD
ILO 0.05 3 µA
Standby current:
I
SB 1.6 4 µA
Power Supply Current, READ: SCL clock frequency = 100 KHz
I
CC
R
0.4 1 mA
Power Supply Current, WRITE: SCL clock frequency = 100 KHz
I
CC
W
23mA
Table 17: Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to VSS; VDDSPD = +1.7V to +3.6V
Parameter/Condition Symbol Min Max Units Notes
SCL LOW to SDA data-out valid
t
AA 0.2 0.9 µs 1
Time the bus must be free before a new transition can start
t
BUF 1.3 µs
Data-out hold time
t
DH 200 ns
SDA and SCL fall time
t
F300ns2
Data-in hold time
t
HD:DAT 0 µs
Start condition hold time
t
HD:STA 0.6 µs
Clock HIGH period
t
HIGH 0.6 µs
Noise suppression time constant at SCL, SDA inputs
t
I50ns
Clock LOW period
t
LOW 1.3 µs
SDA and SCL rise time
t
R0.3µs2
SCL clock frequency
f
SCL 400 KHz
Data-in setup time
t
SU:DAT 100 ns
Start condition setup time
t
SU:STA 0.6 µs 3
Stop condition setup time
t
SU:STO 0.6 µs
WRITE cycle time
t
WRC 10 ms 4
PDF: 09005aef817ab1fc/Source: 09005aef817ab1dd Micron Technology, Inc., reserves the right to change products or specifications without notice.
HTF9C32_64_128x72K.fm - Rev. C 9/06 EN
15 ©2005 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB: (x72, SR) 244-Pin DDR2 Registered MiniDIMM
Register and PLL Specifications
Table 18: Serial Presence-Detect Matrix
“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; table notes located on page 17
Byte Description
Entry
(Version)
MT9HTF3272K/
MT9HTF3272(P)K
MT9HTF6472K/
MT9HTF6472(P)K
MT9HTF12872K/
MT9HTF12872K(P)K
0
Number of SPD bytes used by
Micron
128 80 80 80
1
Total number of bytes in SPD
device
256 08 08 08
2
Fundamental memory type
DDR2 SDRAM 08 08 08
3
Number of row addresses on
assembly
13, 14 0D 0E 0E
4
Number of column addresses on
assembly
10 0A 0A 0A
5
DIMM height and module ranks
30mm,
single rank
60 60 60
6
Module data width
72 48 48 48
7
Module data width (continued)
000 00 00
8
Module voltage interface levels
SSTL 1.8V 05 05 05
9
SDRAM cycle time,
t
CK (CL =
maximum value, see byte 18)
-80E/-800
-667
-53E
-40E
30
3D
50
25
30
3D
50
25
30
3D
50
10
SDRAM access from Clock,
t
AC
(CL = maximum value, see
byte 18)
-80E/-800
-667
-53E
-40E
45
50
60
40
45
50
60
40
45
50
60
11
Module configuration type
ECC
ECC and parity
02
06
02
06
02
06
12
Refresh rate/type
7.81µs/SELF 82 82 82
13
SDRAM device width (primary
SDRAM)
808 08 08
14
Error-checking SDRAM data
width
808 08 08
15
Minimum clock delay, back-to-
back random column access
1 clock 00 00 00
16
Burst lengths supported
4, 8 0C 0C 0C
17
Number of banks on SDRAM
device
4 or 8 04 04 08
18
CAS latencies supported
-80E (5, 4)
-800 (6, 5)
-667 (5, 4, 3)
-53E/-40E (4, 3)
38
18
30
60
38
18
60
60
38
18
19
Module thickness
01 01 01
20
DDR2 DIMM type
Registered
MiniDIMM
10 10 10
21
SDRAM module attributes
04 04 04
22
SDRAM device attributes: weak
driver (01) and 50Ω ODT (03)
-80E/-800/-667
-53E/-40E
–/03
01
03
01
03
01
23
SDRAM cycle time,
t
CK,
MAX CL - 1
-80E/-667
-800
-53E/-40E
–/3D
50
3D
30
50
3D
30
50

MT9HTF6472KY-667B3

Mfr. #:
Manufacturer:
Micron
Description:
MOD DDR2 SDRAM 512MB 244MRDIMM
Lifecycle:
New from this manufacturer.
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