74AVC1T1004
1-to-4 fan-out buffer
Rev. 1 — 23 April 2018 Product data sheet
1 General description
The 74AVC1T1004 is a translating 1-to-4 fan-out buffer suitable for use in clock
distribution. It has dual supplies (V
CC(A)
and V
CC(B)
) for voltage translation. It also has a
data input (A), four data outputs (Yn) and an output enable input (OE). V
CC(A)
and V
CC(B)
can be independently supplied at any voltage between 0.8 V and 3.6 V. It makes the
device suitable for low voltage translation between any of the following voltages: 0.8 V,
1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V. The levels of A and OE are referenced to V
CC(A)
,
outputs Yn are referenced to V
CC(B)
. This supply configuration ensures that the fanned
out signals can be used in level shifting. A HIGH on OE causes all outputs to be pulled
LOW via pull-down resistors, a LOW on OE disconnects the pull-down resistors and
enables all outputs.
Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall
time.
The I
OFF
circuitry disables the output, preventing any damaging backflow current through
the device when it is powered down.
2 Features and benefits
• Wide supply voltage range:
– V
CC(A)
: 0.8 V to 3.6 V
– V
CC(B)
: 0.8 V to 3.6 V
• Complies with JEDEC standards:
– JESD8-12 (0.8 V to 1.3 V)
– JESD8-11 (0.9 V to 1.65 V)
– JESD8-7 (1.2 V to 1.95 V)
– JESD8-5 (1.8 V to 2.7 V)
– JESD8-B (2.7 V to 3.6 V)
• ESD protection:
– HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2 kV
– CDM JESD22-C101 exceeds 1000 V
• Maximum data rates:
– 380 Mbit/s (≥ 1.8 V to 3.3 V translation)
– 200 Mbit/s (≥ 1.1 V to 3.3 V translation)
– 200 Mbit/s (≥ 1.1 V to 2.5 V translation)
– 200 Mbit/s (≥ 1.1 V to 1.8 V translation)
– 150 Mbit/s (≥ 1.1 V to 1.5 V translation)
– 100 Mbit/s (≥ 1.1 V to 1.2 V translation)
• Latch-up performance exceeds 100 mA per JESD 78 Class II
• Inputs accept voltages up to 3.6 V
• Specified from -40 °C to +85 °C and -40 °C to +125 °C
