MAX7032
Low-Cost, Crystal-Based, Programmable,
ASK/FSK Transceiver with Fractional-N PLL
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Envelope Shaping
The MAX7032 features an internal envelope-shaping
resistor, which connects between the open-drain output
of the PA and the power supply (see the
Typical
Application Circuit
). The envelope-shaping resistor
slows the turn-on/turn-off of the PA in ASK mode and
results in a smaller spectral width of the modulated PA
output signal.
Fractional-N PLL
The MAX7032 utilizes a fully integrated fractional-N PLL
for its transmit frequency synthesizer. All PLL compo-
nents, including the loop filter, are included on chip.
The loop bandwidth is approximately 200kHz. The 16-
bit fractional-N topology allows the transmit frequency
to be adjusted in increments of f
XTAL
/4096. The fine-
frequency-adjustment capability enables the use of a
single crystal, as the transmit frequency can be set
within 2kHz of the receive frequency.
The fractional-N topology also allows exact FSK fre-
quency deviations to be programmed, completely elim-
inating the problems associated with generating
frequency deviations by crystal oscillator pulling.
The integer and fractional portions of the PLL divider
ratio set the transmit frequency. The example below
shows how to calculate f
XTAL
and how to determine the
correct values to be loaded to register TxLOW (register
0x0D and 0x0E) and TxHIGH (registers 0x0F and
0x10):
Assume the receiver/ASK transmit frequency = 315MHz
and IF = 10.7MHz:
and
Due to the nature of the transmit PLL frequency divider,
a fixed offset of 16 must be subtracted from the trans-
mit PLL divider ratio for programming the MAX7032’s
transmit frequency registers. To determine the value to
program the MAX7032’s transmit frequency registers,
convert the decimal value of the following equation to
the nearest hexadecimal value:
In this example, the rounded decimal value is 36,225,
or 8D81 hexadecimal. The upper byte (8D) is loaded
into register 0x0D, and the low byte (81) is loaded into
register 0x0E.
In FSK mode, the transmit frequencies equal the upper
and lower frequencies that are programmed into the
MAX7032’s transmit frequency registers. Calculate the
upper frequency in the same way as shown above. In
ASK mode, the transmit frequency equals the lower fre-
quency that is programmed into the MAX7032’s trans-
mit frequency registers.
Power-Supply Connections
The MAX7032 can be powered from a 2.1V to 3.6V
supply or a 4.5V to 5.5V supply. If a 4.5V to 5.5V supply
is used, then the on-chip linear regulator reduces the
5V supply to the 3V needed to operate the chip.
To operate the MAX7032 from a 3V supply, connect
PAVDD, AVDD, DVDD, and HVIN to the 3V supply.
When using a 5V supply, connect the supply to HVIN
only and connect AVDD, PAVDD, and DVDD together.
In both cases, bypass DVDD, PAVDD and HVIN to
GND with a 0.01µF and 220pF capacitor and bypass
AVDD to GND with a 0.1µF and 220pF capacitor.
Bypass T/R, ENABLE, DATA, CS, DIO, and SCLK with
10pF capacitors to GND. Place all bypass capacitors
as close as possible to the respective pins.
Transmit/Receive Antenna Switch
The MAX7032 features an internal SPST RF switch,
which, when combined with a few external compo-
nents, allows the transmit and receive pins to share a
common antenna (see the
Typical Application Circuit)
.
In receive mode, the switch is open and the power
amplifier is shut down, presenting a high impedance to
minimize the loading of the LNA. In transmit mode, the
switch closes to complete a resonant tank circuit at the
PA output and forms an RF short at the input to the
LNA. In this mode, the external passive components
couple the output of the PA to the antenna to protect
the LNA input from strong transmitted signals.
The switch state is controlled either by an external digi-
tal input or by the T/R bit, which is bit 6 in the configura-
tion 0 register, T/R. Drive the T/R pin high to put the
device in transmit mode; drive the T/R pin low to put the
device in receive mode.
(.)
.
