MAX7032
Low-Cost, Crystal-Based, Programmable,
ASK/FSK Transceiver with Fractional-N PLL
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REGISTER A[5:0] REGISTER NAME DESCRIPTION
0x00 Power configuration
Enables/disables the LNA, AGC, mixer, baseband, peak
detectors, PA, and RSSI output (see Table 5).
0x01 Control
Controls AGC lock, gain state, peak-detector tracking, polling
timer and FSK calibration, clock signal output, and sleep mode
(see Table 6).
0x02 Configuration0
Sets options for modulation, TX/RX mode, manual-gain mode,
discontinuous receive mode, off-timer and on-timer prescalers
(see Table 7).
0x03 Configuration1
Sets options for automatic FSK calibration, clock output, output
clock divider ratio, AGC dwell timer (see Tables 8, 10, 11, and 12).
0x05 Oscillator frequency
Sets the internal clock frequency divisor. This register must be set
to the integer result of f
XTAL
/100kHz (see the Oscillator Frequency
Register (Address 0x05) section).
0x06 Off timer—t
OFF
(upper byte)
0x07 Off timer—t
OFF
(lower byte)
Sets the duration that the MAX7032 remains in low-power mode
when DRX is active (see Table 12).
0x08 CPU recovery timer—t
CPU
Increases maximum time the MAX7032 stays in lower power mode
while CPU wakes up when DRX is active (see Table 13).
0x09
RF settling timer—t
RF
(upper
byte)
0x0A
RF settling timer—t
RF
(lower
byte)
During the time set by the RF settling timer, the MAX7032 is
powered on with the peak detectors and the data outputs disabled
to allow time for the RF section to settle. DIO must be driven low at
any time during t
LOW
= t
CPU
+ t
RF
+ t
ON
or the timer sequence
restarts (see Table 14).
0x0B On timer—t
ON
(upper byte)
0x0C On timer—t
ON
(lower byte)
Sets the duration that the MAX7032 remains in active mode when
DRX is active (see Table 15).
0x0D
Transmitter low-frequency
setting—TxLOW (upper byte)
0x0E
Transmitter low-frequency
setting—TxLOW (lower byte)
Sets the low frequency (FSK) of the transmitter or the carrier
frequency of ASK for the fractional-N synthesizer.
0x0F
Transmitter high-frequency
setting—TxHIGH (upper byte)
0x10
Transmitter high-frequency
setting—TxHIGH (lower byte)
Sets the high frequency (FSK) of the transmitter for the fractional-N
synthesizer.
0x1A Status register (read only)
Provides status for PLL lock, AGC state, crystal operation, polling
timer, and FSK calibration (see Table 9).
Table 3. Register Summary
