MAX7032EVSYS-315 Datasheet MAX7032ATJ+, MAX7032EVSYS-315, MAX7032ATJ+T | P22-P24

MAX7032

Low-Cost, Crystal-Based, Programmable,

ASK/FSK Transceiver with Fractional-N PLL

22 ______________________________________________________________________________________

BIT ID BIT NAME BIT LOCATION (0 = LSB) FUNCTION

AGCLK AGC locking feature 7

1 = Enable AGC lock

0 = Disable AGC lock

GAIN Gain state 6

1 = Force manual high-gain state if MGAIN = 1

0 = Force manual low-gain state if MGAIN = 1

TRK_EN

Manual peak-detector

tracking

1 = Force manual peak-detector tracking

0 = Release peak-detector tracking

X None 4 Not used

PCAL Polling timer calibration 3

1 = Perform polling timer calibration

Automatically reset to zero once calibration is completed

FCAL FSK calibration 2

1 = Perform FSK calibration

Automatically reset to zero once calibration is completed

CKOUT Crystal clock output enable 1

1 = Enable crystal clock output

0 = Disable crystal clock output

SLEEP Sleep mode 0

1 = Deep-sleep mode, regardless the state of

ENABLE pin

0 = Normal operation

Table 6. Control Register (Address: 0x01)

BIT ID BIT NAME BIT LOCATION (0 = LSB) FUNCTION

LNA LNA enable 7

1 = Enable LNA

0 = Disable LNA

AGC AGC enable 6

1 = Enable AGC

0 = Disable AGC

MIXER Mixer enable 5

1 = Enable mixer

0 = Disable mixer

BaseB Baseband enable 4

1 = Enable baseband

0 = Disable baseband

PkDet Peak-detector enable 3

1 = Enable peak detector

0 = Disable peak detector

PA Transmitter PA enable 2

1 = Enable PA

0 = Disable PA

RSSIO RSSI amplifier enable 1

1 = Enable buffer

0 = Disable buffer

X None 0 Not used

Table 5. Power-Configuration Register (Address: 0x00)

MAX7032

Low-Cost, Crystal-Based, Programmable,

ASK/FSK Transceiver with Fractional-N PLL

______________________________________________________________________________________ 23

BIT ID BIT NAME BIT LOCATION (0 = LSB) FUNCTION

MODE FSK or ASK modulation 7

1 = Enable FSK for both receive and

transmit

0 = Enable ASK for both receive and

transmit

T/R Transmit or receive 6

1 = Enable transmit mode of the

transceiver, regardless the state of pin

T/R

0 = Enable receive mode of the transceiver

when pin T/R = 0

MGAIN Manual gain mode 5

1 = Enable manual-gain mode

0 = Disable manual-gain mode

DRX

Discontinuous receive

mode

1 = Enable DRX

0 = Disable DRX

OFPS1 Off-timer prescaler 3

OFPS0 Off-timer prescaler 2

Sets the time base for the off timer (see the

Off Timer (t

OFF

)

section)

ONPS1 On-timer prescaler 1

ONPS0 On-timer prescaler 0

Sets the time base for the on timer (see the

On Timer (t

) section)

Table 7. Configuration 0 Register (Address: 0x02)

BIT ID BIT NAME BIT LOCATION (0 = LSB) FUNCTION

X None 7 Not used

ACAL Automatic FSK calibration 6

1 = Enable automatic FSK calibration when

coming out of the sleep state in DRX mode

0 = Disable automatic FSK calibration

CLKOF

Continuous clock output

(even during t

OFF

or when

ENABLE pin is low)

1 = Enable continuous clock output when CKOUT

= 1

0 = Continuous clock output; if CKOUT = 1, clock

output is active during t

(DRX mode) or when

ENABLE pin is high (continuous receive mode)

CDIV1 Crystal divider 4 CLKOUT crystal-divider MSB

CDIV0 Crystal divider 3 CLKOUT crystal-divider LSB

DT2 AGC dwell timer 2 AGC dwell timer MSB

DT1 AGC dwell timer 1 AGC dwell timer

DT0 AGC dwell timer 0 AGC dwell timer LSB

Table 8. Configuration 1 Register (Address: 0x03)

Oscillator Frequency Register (Address 0x05)

The MAX7032 has an internal frequency divider that

divides down the crystal frequency to 100kHz. The

MAX7032 uses the 100kHz clock signal when calibrat-

ing itself and also to set image-rejection frequency. The

hexadecimal value written to the oscillator frequency

XTAL

/100kHz.

For example, if data is being received at 315MHz, the

crystal frequency is 12.67917MHz. Dividing the crystal

frequency by 100kHz and rounding to the nearest inte-

ger gives 127, or 0x7F hex. So for 315MHz, 0x7F would

be written to the oscillator frequency register.

AGC Dwell Timer (Address 0x03)

The AGC dwell timer holds the AGC in low-gain state

for a set amount of time after the power level drops

below the AGC switching threshold. After that set

amount of time, if the power level is still below the AGC

threshold, the LNA goes into high-gain state. This is

important for ASK since the modulated data may have

a high level above the threshold and a low level below

the threshold, which without the dwell timer would

cause the AGC to switch on every bit.

MAX7032

Low-Cost, Crystal-Based, Programmable,

ASK/FSK Transceiver with Fractional-N PLL

24 ______________________________________________________________________________________

CKOUT CDIV1 CDIV0

CLOCKOUT

FREQUENCY

0 X X Disabled at logic 0

10 0f

XTAL

10 1f

XTAL

11 0f

XTAL

11 1f

XTAL

Table 10. Clock Output Divider Ratio

Configuration

BIT ID BIT NAME

BIT LOCATION

(0 = LSB)

FUNCTION

LCKD Lock detect 7

1 = Internal PLL is locked

0 = Internal PLL is not locked so the

MAX7032 does not receive or transmit data

GAINS AGC gain state 6

1 = LNA in high-gain state

0 = LNA in low-gain state

CLKON Clock/crystal alive 5

1 = Valid clock at crystal inputs

0 = No valid clock signal seen at the crystal

inputs

X None 4 Zero

X None 3 Zero

X None 2 Zero

PCALD

Polling timer calibration

done

1 = Polling timer calibration is completed

0 = Polling timer calibration is in progress or

not completed

FCALD FSK calibration done 0

1 = FSK calibration is completed

0 = FSK calibration is in progress or not

completed

Table 9. Status Register (Read Only) (Address: 0x1A)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P32

MAX7032EVSYS-315

Mfr. #:

Buy MAX7032EVSYS-315

Manufacturer:

Maxim Integrated

Description:

RF Development Tools MAX7032 Eval Kit

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MAX7032EVSYS-315

MAX7032EVSYS-315

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