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ISL6269AIRZ

P1-P3P4-P6P7-P9P10-P12P13-P15
ISL6269A
10
FN9253.3
November 18, 2014
Submit Document Feedback
negative voltage across the PHASE and GND pins is nulled by the
voltage dropped across R
SEN
as I
SEN
conducts through it. An OCP
fault occurs if I
SEN
rises above the OCP threshold current I
OC
while attempting to null the negative voltage across the PHASE
and GND pins. I
SEN
must exceed I
OC
on all the PWM pulses that
occur within 20µs. If I
SEN
falls below I
OC
on a PWM pulse before
20µs has elapsed, the timer will be reset. An SCP fault will occur
within 10µs when I
SEN
exceeds twice I
OC.
The relationship
between I
D
and I
SEN
is written as:
The value of R
SEN
is then written as:
Where:
-R
SEN
(Ω) is the resistor used to program the overcurrent
setpoint
-I
SEN
is the current sense current that is sourced from the
ISEN pin
-I
OC
is the I
SEN
threshold current sourced from the ISEN pin
that will activate the OCP circuit
-I
FL
is the maximum continuous DC load current
-I
P-P
is the inductor peak-to-peak ripple current
-OC
SP
is the desired overcurrent setpoint expressed as a
multiplier relative to I
FL
Overvoltage Protection
When an OVP fault is detected, the PGOOD pin will pull down to
60Ω
and latch-off the converter. The OVP fault will remain
latched until V
VCC
has decayed below the falling POR threshold
voltage
V
VCC_THF
.
The OVP fault detection circuit triggers after the voltage across
the FB and GND pins has increased above the rising overvoltage
threshold V
OVR.
Although the converter has latched-off in
response to an OVP fault, the LG gate-driver output will retain the
ability to toggle the low-side MOSFET on and off, in response to
the output voltage transversing the V
OVR
and V
OVF
thresholds.
Undervoltage Protection
When a UVP fault is detected, the PGOOD pin will pull down to
95Ω
and latch-off the converter. The fault will remain latched
until the EN pin has been pulled below the falling EN threshold
voltage V
ENTHF
or if V
VCC
has decayed below the falling POR
threshold voltage
V
VCC_THF
.
The UVP fault detection circuit
triggers after the voltage across the FB and GND pins has fallen
below the undervoltage threshold V
UV
.
Over-Temperature
When the temperature of the ISL6269A increases above the
rising threshold temperature T
OTR
, the IC will enter an OTP state
that suspends the PWM , forcing the LG and UG gate-driver
outputs low. The status of the PGOOD pin does not change nor
does the converter latch-off. The PWM remains suspended until
the IC temperature falls below the hysteresis temperature
T
OTHYS
at which time normal PWM operation resumes. The OTP
state can be reset if the EN pin is pulled below the falling EN
threshold voltage V
ENTHF
or if V
VCC
decays below the falling POR
threshold voltage
V
VCC_THF
. All other protection circuits function
normally during OTP. It is likely that the IC will detect an UVP fault
because in the absence of PWM, the output voltage immediately
decays below the undervoltage threshold V
UV
; the PGOOD pin will
pull down to 95Ω
and latch-off the converter. The UVP fault will
remain latched until the EN pin has been pulled below the falling
EN threshold voltage V
ENTHF
or if V
VCC
has decayed below the
falling POR threshold voltage
V
VCC_THF
.
Programming the Output Voltage
When the converter is in regulation there will be 600mV from the
FB pin to the GND pin. Connect a two-resistor voltage divider
across the VO pin and the GND pin with the output node
connected to the FB pin. Scale the voltage-divider network such
that the FB pin is 600mV with respect to the GND pin when the
converter is regulating at the desired output voltage. The output
voltage can be programmed from 600mV to 3.3V.
Programming the output voltage is written as:
Where:
-V
OUT
is the desired output voltage of the converter
-V
REF
is the voltage that the converter regulates to between
the FB pin and the GND pin
-R
TOP
is the voltage-programming resistor that connects
from the FB pin to the VO pin. In addition to setting the
output voltage, this resistor is part of the loop compensation
network
-R
BOTTOM
is the voltage-programming resistor that connects
from the FB pin to the GND pin
Beginning with R
TOP
between 1kΩ to 5kΩcalculating R
BOTTOM
is written as:
Programming the PWM Switching Frequency
The ISL6269A does not use a clock signal to produce PWM. The
PWM switching frequency f
SW
is programmed by the resistor
R
FSET
that is connected from the FSET pin to the GND pin. The
approximate PWM switching frequency is written as:
Estimating the value of R
FSET
is written as:
Where:
-f
SW
is the PWM switching frequency
-R
FSET
is the f
SW
programming resistor
-K = 75 x 10
-12
It is recommended that whenever the control loop compensation
network is modified, f
SW
should be checked for the correct
frequency and if necessary, adjust R
FSET
.
I
SEN
R
SEN
I
D
r
DS ON
=
(EQ. 3)
(EQ. 4)
R
SEN
I
FL
I
P-P
2
----------
+


OC
SP
r
DS ON
I
OC
------------------------------------------------------------------------------
=
V
REF
V
OUT
R
BOTTOM
R
TOP
R
BOTTOM
+
---------------------------------------------------
=
(EQ. 5)
R
BOTTOM
V
REF
R
TOP
V
OUT
V
REF
–
-------------------------------------
=
(EQ. 6)
f
SW
1
KR
FSET
---------------------------
=
(EQ. 7)
R
FSET
1
Kf
SW
------------------
=
(EQ. 8)
ISL6269A
11
FN9253.3
November 18, 2014
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Compensation Design
The LC output filter has a double pole at its resonant frequency that
causes the phase to abruptly roll downward. The R3™ Modulator
used in the ISL6269A makes the LC output filter resemble a first
order system in which the closed loop stability can be achieved with
a Type II compensation network.
Your local Intersil representative can provide a PC-based tool that
can be used to calculate compensation network component
values and help simulate the loop frequency response. The
compensation network consists of the internal error amplifier of the
ISL6269A and the external components R
1
, R
2
, C
1
and C
2
as well
as the frequency setting components R
FSET
and C
FSET
are
identified in the schematic Figure 6
.
General Application Design
Guide
This design guide is intended to provide a high-level explanation of
the steps necessary to create a single-phase power converter. It is
assumed that the reader is familiar with many of the basic skills
and techniques referenced. In addition to this guide, Intersil
provides complete reference designs that include schematics, bills
of materials, and example board layouts.
Selecting the LC Output Filter
The duty cycle of an ideal buck converter is a function of the
input and the output voltage. This relationship is written as:
The output inductor peak-to-peak ripple current is written as:
A typical step-down DC/DC converter will have an I
P-P
of 20% to
40% of the maximum DC output load current. The value of I
P-P
is
selected based upon several criteria such as MOSFET switching
loss, inductor core loss and the resistive loss of the inductor
winding. The DC copper loss of the inductor can be estimated by:
Where I
LOAD
is the converter output DC current.
The copper loss can be significant so attention has to be given to
the DCR selection. Another factor to consider when choosing the
inductor is its saturation characteristics at elevated temperature.
A saturated inductor could cause destruction of circuit
components, as well as nuisance OCP faults.
A DC/DC buck regulator must have output capacitance C
OUT
into
which ripple current I
P-P
can flow. Current I
P-P
develops a
corresponding ripple voltage V
P-P
across C
OUT,
which is the sum
of the voltage drop across the capacitor ESR and of the voltage
change stemming from charge moved in and out of the
capacitor. These two voltages are written as:
and
If the output of the converter has to support a load with high
pulsating current, several capacitors will need to be paralleled to
reduce the total ESR until the required V
P-P
is achieved. The
inductance of the capacitor can cause a brief voltage dip if the
load transient has an extremely high slew rate. Low inductance
capacitors constructed with reverse package geometry are
available. A capacitor dissipates heat as a function of RMS current
and frequency. Be sure that I
P-P
is shared by a sufficient quantity
of paralleled capacitors so that they operate below the maximum
rated RMS current at f
SW
. Take into account that the rated value of
a capacitor can fade as much as 50% as the DC voltage across it
increases.
GND
PHASE
UG
LG
C
OUT
L
OUT
ISL6269A
Q
HIGH_SIDE
R
FSET
C
FSET
Q
LOW_SIDE
EA
+
VIN
VIN
VO
FB
R
2
R
1
C
1
C
2
-
FSET
COMP
REF
C
ESR
GATE DRIVERS
DCR
R3™ MODULATOR
VOUT
FIGURE 6. COMPENSATION REFERENCE CIRCUIT
D
V
OUT
V
IN
----------------
=
(EQ. 9)
(EQ. 10)
I
PP
V
OUT
1D–
f
SW
L
OUT
--------------------------------------
=
(EQ. 11)
P
COPPER
I
LOAD
2
DCR=
V
ESR
I
P-P
E SR=
(EQ. 12)
V
C
I
P-P
8C
OUT
f
SW
-------------------------------------
=
(EQ. 13)
ISL6269A
12
FN9253.3
November 18, 2014
Submit Document Feedback
Selection of the Input Capacitor
The important parameters for the bulk input capacitance are the
voltage rating and the RMS current rating. For reliable operation,
select bulk capacitors with voltage and current ratings above the
maximum input voltage and capable of supplying the RMS
current required by the switching circuit. Their voltage rating
should be at least 1.25 times greater than the maximum input
voltage, while a voltage rating of 1.5 times is a preferred rating.
Figure 7
is a graph of the input RMS ripple current, normalized
relative to output load current, as a function of duty cycle that is
adjusted for converter efficiency. The ripple current calculation is
written as:
Where:
-I
MAX
is the maximum continuous I
LOAD
of the converter
- x is a multiplier (0 to 1) corresponding to the inductor peak-
to-peak ripple amplitude expressed as a percentage of I
MAX
(0% to 100%)
- D is the duty cycle that is adjusted to take into account the
efficiency of the converter which is written as:
In addition to the bulk capacitance, some low ESL ceramic
capacitance is recommended to decouple between the drain of
the high-side MOSFET and the source of the low-side MOSFET.
MOSFET Selection and Considerations
Typically, a MOSFET cannot tolerate even brief excursions beyond
their maximum drain-to-source voltage rating. The MOSFETs used
in the power stage of the converter should have a maximum V
DS
rating that exceeds the sum of the upper voltage tolerance of the
input power source and the voltage spike that occurs when the
MOSFET switches off.
There are several power MOSFETs readily available that are
optimized for DC/DC converter applications. The preferred
high-side MOSFET emphasizes low switch charge so that the
device spends the least amount of time dissipating power in the
linear region. Unlike the low-side MOSFET which has the
drain-to-source voltage clamped by its body diode during turn off,
the high-side MOSFET turns off with V
IN
-V
OUT
-V
L
across it. The
preferred low-side MOSFET emphasizes low r
DS(ON)
when fully
saturated to minimize conduction loss.
For the low-side MOSFET, (LS), the power loss can be assumed to
be conductive only and is written as:
For the high-side MOSFET, (HS), its conduction loss is written as:
For the high-side MOSFET, its switching loss is written as:
Where:
-I
VALLEY
is the difference of the DC component of the
inductor current minus 1/2 of the inductor ripple current
-I
PEAK
is the sum of the DC component of the inductor
current plus 1/2 of the inductor ripple current
-t
ON
is the time required to drive the device into saturation
-t
OFF
is the time required to drive the device into cut-off
Selecting The Bootstrap Capacitor
The selection of the bootstrap capacitor is written as:
Where:
-Q
g
is the total gate charge required to turn on the high-side
MOSFET
- V
BOOT
, is the maximum allowed voltage decay across the
boot capacitor each time the high-side MOSFET is switched
on
As an example, suppose the high-side MOSFET has a total gate
charge Q
g
, of 25nC at V
GS
= 5V, and a V
BOOT
of 200mV. The
calculated bootstrap capacitance is 0.125µF. For a comfortable
margin select a capacitor that is double the calculated
capacitance, in this example 0.22µF will suffice. Use an X7R or
X5R ceramic capacitor.
(EQ. 14)
I
IN_RMS
I
MAX
2
DD
2
–xI
MAX
2
D
12
------



+
I
MAX
-----------------------------------------------------------------------------------------------------
=
D
V
OUT
V
IN
EFF
--------------------------
=
(EQ. 15)
FIGURE 7. NORMALIZED RMS INPUT CURRENT FOR x = 0.8
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
DUTY CYCLE
NORMALIZED INPUT RMS RIPPLE CURRENT
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
x = 1
x = 0.75
x = 0.50
x = 0.25
x = 0
(EQ. 16)
P
CON_LS
I
LOAD
2
r
DS ON_LS
1D–
(EQ. 17)
P
CON_HS
I
LOAD
2
r
DS ON_HS
D=
(EQ. 18)
P
SW_HS
V
IN
I
VALLEY
t
ON
f
SW
2
-----------------------------------------------------------------
V
IN
I
PEAK
t
OFF
f
SW
2
-------------------------------------------------------------
+=
C
BOOT
Q
g
V
BOOT
------------------------
=
(EQ. 19)
P1-P3P4-P6P7-P9P10-P12P13-P15

ISL6269AIRZ

Mfr. #:
Buy ISL6269AIRZ
Manufacturer:
Renesas / Intersil
Description:
Switching Controllers GPU CNTRLR 16LD 4X4
Lifecycle:
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