ISL6269A
13
FN9253.3
November 18, 2014
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Layout Considerations
As a general rule, power should be on the bottom layer of the
PCB and weak analog or logic signals are on the top layer of the
PCB. The ground-plane layer should be adjacent to the top layer to
provide shielding. The ground plane layer should have an island
located under the IC, the compensation components and the FSET
components. The island should be connected to the rest of the
ground plane layer at one point.
Signal Ground and Power Ground
The bottom of the ISL6269A QFN package is the signal ground
(GND) terminal for analog and logic signals of the IC. Connect the
GND pad of the ISL6269A to the island of ground plane under the
top layer using several vias, for a robust thermal and electrical
conduction path. Connect the input capacitors, the output
capacitors, and the source of the lower MOSFETs to the power
ground plane.
PGND (Pin 10)
This is the return path for the pull-down of the LG low-side
MOSFET gate driver. Ideally, PGND should be connected to the
source of the low-side MOSFET with a low-resistance, low-
inductance path .
VIN (Pin 1)
The VIN pin should be connected close to the drain of the high-
side MOSFET, using a low resistance and low inductance path.
VCC (Pin 2)
For best performance, place the decoupling capacitor very close
to the VCC and GND pins.
PVCC (Pin 12)
For best performance, place the decoupling capacitor very close
to the PVCC and PGND pins, preferably on the same side of the
PCB as the ISL6269A IC.
FCCM (Pin 3), EN (Pin 4), PGOOD (Pin 16)
These are logic inputs that are referenced to the GND pin. Treat
as a typical logic signal.
COMP (Pin 5), FB (Pin 6), VO (Pin 8)
For best results, use an isolated sense line from the output load
to the VO pin. The input impedance of the FB pin is high, so place
the voltage programming and loop compensation components
close to the VO, FB, and GND pins keeping the high impedance
trace short.
FSET (Pin 7)
This pin requires a quiet environment. The resistor R
FSET
and
capacitor C
FSET
should be placed directly adjacent to this pin.
Keep fast moving nodes away from this pin.
ISEN (Pin 9)
Route the connection to the ISEN pin away from the traces and
components connected to the FB pin, COMP pin, and FSET pin.
LG (Pin 11)
The signal going through this trace is both high dv/dt and high
di/dt, with high peak charging and discharging current. Route
this trace in parallel with the trace from the PGND pin. These two
traces should be short, wide, and away from other traces. There
should be no other weak signal traces in proximity with these
traces on any layer.
BOOT (Pin 13), UG (Pin 14), PHASE (Pin 15)
The signals going through these traces are both high dv/dt and
high di/dt, with high peak charging and discharging current.
Route the UG and PHASE pins in parallel with short and wide
traces. There should be no other weak signal traces in proximity
with these traces on any layer.
Copper Size for the Phase Node
The parasitic capacitance and parasitic inductance of the phase
node should be kept very low to minimize ringing. It is best to
limit the size of the PHASE node copper in strict accordance with
the current and thermal management of the application. An
MLCC should be connected directly across the drain of the upper
MOSFET and the source of the lower MOSFET to suppress the
turn-off voltage spike.
INDUCTOR
VIAS TO
GROUND
PLANE
VIN
VOUT
PHASE
NODE
GND
OUTPUT
CAPACITORS
LOW-SIDE
MOSFETS
INPUT
CAPACITORS
SCHOTTKY
DIODE
HIGH-SIDE
MOSFETS
FIGURE 8. TYPICAL POWER COMPONENT PLACEMENT
