ISL6269A
9
FN9253.3
November 18, 2014
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impedance if V
VCC
has not reached the rising POR threshold
V
VCC_THR
, or if V
VCC
is below the falling POR threshold V
VCC_THF
.
The ISL6269A features a unique fault-identification capability
that can drastically reduce troubleshooting time and effort. The
pull-down resistance of the PGOOD pin corresponds to the fault
status of the controller. During soft-start or if an undervoltage
fault occurs, the PGOOD pull-down resistance is 95Ω, or 30Ω for
an overcurrent fault, or 60Ω for an overvoltage fault.
MOSFET Gate-Drive Outputs LG and UG
The ISL6269A has internal gate drivers for the high-side and low-
side N-Channel MOSFETs. The LG gate driver is optimized for low
duty-cycle applications where the low-side MOSFET conduction
losses are dominant, requiring a low r
DS(ON)
MOSFET. The LG
pull-down resistance is small in order to clamp the gate of the
MOSFET below the V
GS(th)
at turnoff. The current transient
through the gate at turnoff can be considerable because the
switching charge of a low r
DS(ON)
MOSFET can be large. Adaptive
shoot-through protection prevents a gate-driver output from
turning on until the opposite gate-driver output has fallen below
approximately 1V. The dead-time shown in Figure 5
is extended
by the additional period that the falling gate voltage stays above
the 1V threshold. The high-side gate-driver output voltage is
measured across the UG and PHASE pins while the low-side
gate-driver output voltage is measured across the LG and PGND
pins. The power for the LG gate driver is sourced directly from the
PVCC pin. The power for the UG gate driver is sourced from a
“boot” capacitor connected across the BOOT and PHASE pins.
The boot capacitor is charged from a 5V bias supply through a
“boot diode” each time the low-side MOSFET turns on, pulling the
PHASE pin low. The ISL6269A has an integrated boot diode
connected from the PVCC pin to the BOOT pin.
Diode Emulation
The ISL6269A normally operates in Continuous Conduction
Mode (CCM), minimizing conduction losses by forcing the
low-side MOSFET to operate as a synchronous rectifier. An
improvement in light-load efficiency is achieved by allowing the
converter to operate in Diode Emulation Mode (DEM), where the
low-side MOSFET behaves as a smart-diode, forcing the device to
block negative inductor current flow. The ISL6269A can be
configured to operate in DEM by setting the FCCM pin low.
Setting the FCCM pin high will disable DEM.
Positive-going inductor current flows from either the source of
the high-side MOSFET, or the drain of the low-side MOSFET.
Negative-going inductor current usually flows into the drain of the
low-side MOSFET. When the low-side MOSFET conducts positive
inductor current, the phase voltage will be negative with respect
to the GND and PGND pins. Conversely, when the low-side
MOSFET conducts negative inductor current, the phase voltage
will be positive with respect to the GND and PGND pins. Negative
inductor current occurs when the output load current is less than
½ the inductor ripple current. Sinking negative inductor current
through the low-side MOSFET lowers efficiency through
unnecessary conduction losses. Efficiency can be further
improved with a reduction of unnecessary switching losses by
reducing the PWM frequency. It is characteristic of the R3™
architecture for the PWM frequency to decrease while in diode
emulation. The extent of the frequency reduction is proportional
to the reduction of load current. Upon entering DEM, the PWM
frequency makes an initial step-reduction because of a 33%
step-increase of the window voltage V
W
.
With FCCM pulled low, the converter will automatically enter DEM
after the PHASE pin has detected positive voltage, while the LG
gate-driver pin is high for eight consecutive PWM pulses. The
converter will return to CCM on the following cycle after the
PHASE pin detects negative voltage, indicating that the body
diode of the low-side MOSFET is conducting positive inductor
current.
Overcurrent and Short-Circuit Protection
The Overcurrent Protection (OCP) and short-circuit protection
(SCP) setpoint is programmed with resistor R
SEN
that is
connected across the ISEN and PHASE pins. The PHASE pin is
connected to the drain terminal of the low-side MOSFET.
The SCP setpoint is internally set to twice the OCP setpoint. When
an OCP or SCP fault is detected, the PGOOD pin will pull down to
30Ω
and latch off the converter. The fault will remain latched
until the EN pin has been pulled below the falling EN threshold
voltage V
ENTHF
or if V
VCC
has decayed below the falling POR
threshold voltage
V
VCC_THF
.
The OCP circuit does not directly detect the DC load current
leaving the converter. The OCP circuit detects the peak of
positive-flowing output inductor current. The low-side MOSFET
drain current I
D
is assumed to be equal to the positive output
inductor current when the high-side MOSFET is off. The inductor
current develops a negative voltage across the r
DS(ON)
of the
low-side MOSFET that is measured shortly after the LG
gate-driver output goes high. The ISEN pin sources the OCP sense
current I
SEN,
through the OCP programming resistor R
SEN,
forcing the ISEN pin to zero volts with respect to the GND pin. The
TABLE 1. PGOOD PULL-DOWN RESISTANCE
CONDITION PGOOD RESISTANCE
VCC Below POR Undefined
Soft Start or Undervoltage 95Ω
Overvoltage 60Ω
Overcurrent 30Ω
FIGURE 5. LG AND UG DEAD-TIME
UG
LG
50%
50%
t
LGFUGR
t
UGFLGR
