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8516FYILFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
ICS8516I REVISION B SEPTEMBER 10, 2009 10 ©2009 Integrated Device Technology, Inc.
ICS8516I Data Sheet LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
FIGURE 2C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 2B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both signals must meet the V
PP
and V
CMR
input requirements.
Figures 2A to 2E
show interface
examples for the HiPerClockS CLK/nCLK input driven by the
most common driver types. The input interfaces suggested here
are examples only. Please consult with the vendor of the driver
FIGURE 2A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
IDT HIPERCLOCKS LVHSTL DRIVER
component to confirm the driver termina-tion requirements. For
example in Figure 2A, the input termination applies for IDT
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
FIGURE 2E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
Zo = 50 Ohm
R3
125
HiPerClockS
CLK
nCLK
3.3V
R5
100 - 200
3.3V
R2
84
3.3V
R6
100 - 200
Input
R5,R6 locate near the driver pin.
Zo = 50 Ohm
R1
84
R4
125
C2
LVPECL
C1
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driver
Zo = 50 Ohm
Receiver
CLK
nCLK
3.3V
ICS8516I REVISION B SEPTEMBER 10, 2009 11 ©2009 Integrated Device Technology, Inc.
ICS8516I Data Sheet LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
FIGURE 3. ICS8516I LVDS BUFFER SCHEMATIC EXAMPLE
C5
0.1u
(U1-12)
Zo = 50 Ohm
Zo = 50 Ohm
(U1-25)
LVDS_input
+
-
(U1-31)
Zo = 50 Ohm
C3
0.1u
C6
0.1u
U1
8516
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
36
35
34
33
32
31
30
29
28
27
26
25
48
47
46
45
44
43
42
41
40
39
38
37
VDD
nQ5
Q5
nQ4
Q4
VDD
GND
nQ3
Q3
nQ2
Q2
VDD
nQ1
Q1
nQ0
Q0
GND
nCLK
CLK
GND
Q15
nQ15
Q14
nQ14
VDD
nQ10
Q10
nQ11
Q11
VDD
GND
nQ12
Q12
nQ13
Q13
VDD
Q6
nQ6
Q7
nQ7
GND
OE1
OE2
GND
nQ8
Q8
nQ9
Q9
Zo = 50 Ohm
R16
100
Zo = 50 Ohm
VDD=3.3V
LVDS_input
+
-
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
VDD=3.3V
R10
100
C4
0.1u
C2
0.1u
LVDS_Driver
R17
100
LVDS_input
+
-
(U1-1)
Decoupling capacitors located near the power pins
(U1-6) (U1-36)
R1
100
C1
0.1u
SCHEMATIC EXAMPLE
Figure 3
shows a schematic example of ICS8516I. In this example,
the input is driven by an LVDS driver. For LVDS buffer, it is
recommended to terminate the unused outputs for better signal
integrity. The decoupling capacitors should be physically located
near the power pin.
ICS8516I REVISION B SEPTEMBER 10, 2009 12 ©2009 Integrated Device Technology, Inc.
ICS8516I Data Sheet LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
LVDS DRIVER T ERMINATION
A general LVDS interface is shown in
Figure 4.
In a 100Ω
differential transmission line environment, LVDS drivers require
a matched load termination of 100Ω across near the receiver
input. For a multiple LVDS outputs buffer, if only partial outputs
are used, it is recommended to terminate the unused outputs.
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
3.3V
R1
100
Zo = 50 Ohm
LVDS_Driver
HiPerClockS
CLK
nCLK
Zo = 50 Ohm
3.3V
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

8516FYILFT

Mfr. #:
Buy 8516FYILFT
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 16 LVDS OUT BUFFER
Lifecycle:
New from this manufacturer.
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