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8516FYILFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
ICS8516I REVISION B SEPTEMBER 10, 2009 4 ©2009 Integrated Device Technology, Inc.
ICS8516I Data Sheet LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V
DD
= 3.3V±5%, TA = -40°C TO 85°C
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, V
DD
= 3.3V±5%, TA = -40°C TO 85°C
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, V
DD
= 3.3V±5%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
DD
egatloVylppuSevitisoP 531.33.3564.3V
I
DD
tnerruCylppuSrewoPcitatS
R
L
001= Ω 581Am
daoLoN08Am
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
I
HI
tnerruChgiHtupnI
KLCV
NI
V=
DD
V564.3=051Aµ
KLCnV
NI
V=
DD
V564.3=5Aµ
I
LI
tnerruCwoLtupnI
KLCV
DD
V,V564.3=
NI
V0=5-Aµ
KLCnV
DD
V,V564.3=
NI
V0=051-Aµ
V
PP
egatloVkaeP-ot-kaeP 51.03.1V
V
RMC
;egatloVtupnIedoMnommoC
2,1ETON
5.0+DNGV
DD
58.0-V
VsiKLCn,KLCrofegatlovtupnimumixameht,snoitacilppadedneelgnisroF:1ETON
DD
.V3.0+
tsadenifedsiegatlovedomnommoC:2ETONV
HI
.
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V
HI
egatloVhgiHtupnI2EO,1EO2V
DD
3.0+V
V
LI
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I
HI
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DD
V=
NI
V564.3=5Aµ
I
LI
tnerruCwoLtupnI2EO,1EOV
DD
V,V564.3=
NI
V0=051-Aµ
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, I
O
Continuous Current 10mA
Surge Current 15mA
Package Thermal Impedance, θ
JA
47.9°C/W (0 lfpm)
Storage Temperature, T
STG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
ICS8516I REVISION B SEPTEMBER 10, 2009 5 ©2009 Integrated Device Technology, Inc.
ICS8516I Data Sheet LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
TABLE 5. AC CHARACTERISTICS, V
DD
= 3.3V±5%, TA = -40°C TO 85°C
TABLE 4D. LVDS DC CHARACTERISTICS, V
DD
= 3.3V±5%, TA = -40°C TO 85°C
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DO
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SO
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Δ V
SO
V
SO
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I
ZO
tnerruCegakaeLecnadepmIhgiH 01-01+Aµ
I
FFO
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I
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I
SO
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ICS8516I REVISION B SEPTEMBER 10, 2009 6 ©2009 Integrated Device Technology, Inc.
ICS8516I Data Sheet LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
ADDITIVE PHASE JITTER
Additive Phase Jitter @
155.52MHz (12kHz to 20MHz)
= 148fs typical
-50
-60
-70
-80
-90
-100
-100
-120
-130
-140
-150
-160
1k 10k 100k 1M 10M 100M
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the
dBc Phase Noise.
This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz
As with most timing specifications, phase noise measurements
has issues relating to the limitations of the equipment. Often the
noise floor of the equipment is higher than the noise floor of the
band to the power in the fundamental. When the required offset
is specified, the phase noise is called a
dBc
value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
device. This is illustrated above. The device meets the noise floor
of what is shown, but can actually be lower. The phase noise is
dependent on the input source and measurement equipment.
OFFSET FROM CARRIER FREQUENCY (HZ)
SSB PHASE NOISE dBc/HZ
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

8516FYILFT

Mfr. #:
Buy 8516FYILFT
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 16 LVDS OUT BUFFER
Lifecycle:
New from this manufacturer.
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