AD5379ABC Datasheet AD5379ABC, AD5379ABCZ, EVAL-AD5379EBZ | P19-P21

AD5379

Rev. B | Page 18 of 28

FUNCTIONAL DESCRIPTION

DAC ARCHITECTURE—GENERAL

The AD5379 contains 40 DAC channels and 40 output

amplifiers in a single package. The architecture of a single DAC

channel consists of a 14-bit resistor-string DAC followed by an

output buffer amplifier. The resistor-string section is simply a

string of resistors, each of value R, from V

REF

(+) to AGND. This

type of architecture guarantees DAC monotonicity. The 14-bit

binary digital code loaded to the DAC register determines at

which node on the string the voltage is tapped off before being

fed into the output amplifier. The output amplifier translates the

output of the DAC to a wider range. The DAC output is gained

up by a factor of 3.5 and offset by the voltage on the V

REF

(−) pin.

See the Transfer Function section for more information.

CHANNEL GROUPS

The 40 DAC channels on the AD5379 are arranged into four

groups (A, B, C, D) of 10 channels. In each group, eight

channels are connected to V

REF

1(+) and V

REF

1(−), and the

remaining two channels are connected to V

REF

2(+) and

REF

2(−). Each group has two individual REFGND pins. For

example, in Group A, eight channels are connected to

REFGNDA1, and the remaining two channels are connected to

REFGNDA2. In addition to an input register (x1) and a DAC

the user to calibrate out errors in the complete signal chain,

including the DAC errors.

Table 9 shows the reference and REFGND inputs, and the

m and c registers for Group A. Groups B, C, and D are similar.

Table 9. Inputs and Registers for Group A

Channel Reference REFGND m, c Registers

0 to 7 V

REF

1(+), V

REF

1(−) REFGNDA1 m REG0 to REG7

c REG0 to REG7

8 and 9 V

REF

2(+), V

REF

2(−) REFGNDA2 m REG8 and REG9

c REG8 and REG9

TRANSFER FUNCTION

The digital input transfer function for each DAC can be

represented as

x2 = [(m + 1)/2

× x1] + (c − 2

n−1

)

where:

x2 is the data-word loaded to the resistor string DAC.

(Default is 10 0000 0000 0000.)

x1 is the 14-bit data-word written to the DAC input register.

(Default is 10 0000 0000 0000.)

m is the 13-bit gain coefficient. (Default is 1 1111 1111 1111.)

c is the 14-bit offset coefficient. (Default is 10 0000 0000 0000.)

n is the DAC resolution (n = 14).

Figure 19 shows a single DAC channel and its associated

registers. The power-on values for the m and c registers are full

scale and 0x2000, respectively. The user can individually adjust

the voltage range on each DAC channel by overwriting the

power-on values of m and c. The AD5379 has digital overflow

and underflow detection circuitry to clamp the DAC output at

full scale or zero scale when the values chosen for x1, m, and c

result in x2 being out of range.

DACx2

REF

(+)

AGND

REG

x1 INPUT

REG

DAC

m REG

c REG

INPUT

DATA

VDAC

DAC

REG

LDAC

03165-019

Figure 19. Single DAC Channel

The complete transfer function for the AD5379 can be

represented as

VOUT = 3.5 × ((VREF(+)− AGND) × x2/2

) +

2.5 × (VREF(−)− AGND) + REFGND

where:

x2 is the data word loaded to the resistor string DAC.

REF

(+) is the voltage at the positive reference pin.

REF

(−) is the voltage at the negative reference pin.

Figure 20 shows the output amplifier stage of a single channel.

VDAC is the voltage output from the resistor string DAC. The

nominal range of VDAC is 1 LSB to full scale.

VDAC

2.5R

VOUT

REF

(–)

REFGND

AGND

03165-020

Figure 20. Output Amplifier Stage

AD5379

Rev. B | Page 19 of 28

BIAS

FUNCTION

The AD5379 has an on-chip voltage generator that provides a

bias voltage of 4.25 V (minimum). The V

BIAS

pin is provided for

bypassing and overdriving purposes only. It is not intended to

be used as a supply or a reference. If V

REF

(+) > 4.25 V, V

BIAS

must

be pulled high externally to an equal or higher potential (such

as 5 V). The external voltage source should be capable of

driving a 50 μA (typical) current sink load.

REFERENCE SELECTION

The voltages applied to V

REF

(+) and V

REF

(−) determine the

output voltage range and span on VOUT0 to VOUT39. If the

offset and gain features are not used (m and c are left at their

power-on values), the required reference levels can be

calculated as follows:

VREF(+)

min

= (VOUT

max

− VOUT

min

)/3.5

VREF(−)

max

= (AGND + VOUT

min

)/2.5

If the offset and gain features of the AD5379 are used, then the

required output range is slightly different. The chosen output

range should take into account the offset and gain errors that

need to be trimmed out. Therefore, the chosen output range

should be larger than the actual, required range.

The required reference levels can be calculated as follows:

1. Identify the nominal output range on VOUT.

2. Identify the maximum offset span and the maximum gain

required on the full output signal range.

3. Calculate the new maximum output range on VOUT

including the expected, maximum offset and gain errors.

4. Choose the new required VOUT

max

and VOUT

min

, keeping

the new VOUT limits centered on the nominal values and

assuming REFGND is zero (or equal to AGND). Note that

and V

must provide sufficient headroom.

5. Calculate the values of V

REF

(+) and V

REF

(−) as follows:

REF

(+)

min

= (VOUT

max

− VOUT

min

)/3.5

REF

(−)

max

= (AGND + VOUT

min

)/2.5

In addition, when using reference values other than those

suggested (V

REF

(+) = 5 V and V

REF

(−) = −3.5 V), the expected

offset error component changes to

OFFSET

= 0.125 × (V

REF

(−)

+ 0.7 × V

REF

(+)

)

where:

REF

(−)

is the new negative reference value.

REF

(+)

is the new positive reference value.

If this offset error is too large to calibrate, then adjust the

negative reference value to account for this using the following

equation:

REF

(−)

NEW

= V

REF

(−)

− V

OFFSET

/2.625

Reference Selection Example

Nominal Output Range = 10 V; (−2 V to +8 V)

Offset Error = ±100 mV;

Gain Error = ±3%;

REFGND = AGND = 0 V;

1) Gain Error = ±3%;

=> Maximum Positive Gain Error = +3%

=> Output Range incl. Gain Error = 10 + 0.03(10) = 10.3 V

2) Offset Error = ±100 mV;

=> Maximum Offset Error Span = 2(100) mV = 0.2 V

=> Output Range including Gain Error and

Offset Error = 10.3 + 0.2 = 10.5 V

3) V

REF

(+) and V

REF

(−) Calculation:

Actual Output Range = 10.5 V, that is, −2.25 V to +8.25 V

(centered);

=> V

REF

(+) = (8.25 + 2.25)/3.5 = 3 V

REF

(−) = −2.25/+2.5 = −0.9 V

If the solution yields inconvenient reference levels, the user can

adopt one of three approaches:

• Use a resistor divider to divide down a convenient, higher

reference level to the required level.

• Select convenient reference levels above V

REF

(+)

min

or below

REF

(−)

max

. Modify the gain and offset registers to digitally

downsize the references. In this way, the user can use

almost any convenient reference level, but may reduce

performance by overcompaction of the transfer function.

• Use a combination of these two approaches.

AD5379

Rev. B | Page 20 of 28

CALIBRATION

The user can perform a system calibration by overwriting the

default values in the m and c registers for any individual DAC

channel as follows:

• Calculate the nominal offset and gain coefficients for the

new output range (see previous example).

• Calculate the new m and c values for each channel based

on the specified offset and gain errors.

Calibration Example

Nominal Offset Coefficient = 0

Nominal Gain Coefficient =

10/10.5 × 8191 = 0.95238 × 8191 = 7801

Example 1: Channel 0, Gain Error = 3%, Offset Error = 100 mV

1) Gain Error (3%) Calibration: 7801 × 1.03 = 8035

=> Load Code “1 1111 0110 0011” to m Register 0

2) Offset Error (100 mV) Calibration:

LSB Size = 10.5/16384 = 641 μV;

Offset Coefficient for 100 mV Offset = 100/0.64 = 156 LSBs

=> Load “10 0000 1001 1100” to c Register 0

Example 2: Channel 1, Gain Error = −3%, Offset Error = −100 mV

1) Gain Error (−3%) Calibration: 7801 × 0.97 = 7567

=> Load Code “1 1110 1000 1111” to m Register 1

2) Offset Error (−100 mV) Calibration:

LSB Size = 10.5/16384 = 641 μV;

Offset Coefficient for −100 mV Offset = −100/0.64 = −156 LSBs

=> Load “01 1111 0110 0100” to c Register 1

CLEAR FUNCTION

The clear function on the AD5379 can be implemented in

hardware or software.

Hardware Clear

Bringing the

CLR

pin low switches the outputs, VOUT0 to

VOUT39, to the externally set potential on the REFGND pin.

This is achieved by switching in REFGND and reconfiguring

the output amplifier stages into unity gain buffer mode, thus

ensuring VOUT = REFGND. The contents of the input registers

and DAC registers are not affected by taking

CLR

low. When

CLR

is brought high, the DAC outputs remain cleared until

LDAC

is taken low. While

CLR

is low, the value of

LDAC

ignored.

Software Clear

Loading a clear code to the x1 registers also enables the user to

set VOUT0 to VOUT39 to the REFGND level. The default clear

code corresponds to m at full-scale and c at midscale (x2 = x1).

Default Clear Code

= 2

× (−Output Offset)/(Output Range)

= 2

× 2.5 × (AGND − V

REF

(−))/(3.5 × (V

REF

(+)− AGND))

The more general expression for the clear code is as follows:

Clear Code = (2

)/(m + 1) × (Default Clear Code − c)

BUSY AND LDAC FUNCTIONS

The value of x2 is calculated each time the user writes new data

to the corresponding x1, c, or m registers. During the calcula-

tion of x2, the

BUSY

output goes low. While

BUSY

is low, the

user can continue writing new data to the x1, m, or c registers,

but no DAC output updates can take place. The DAC outputs

are updated by taking the

LDAC

input low. If

LDAC

goes low

while

BUSY

is active, the

LDAC

event is stored and the DAC

outputs update immediately after

BUSY

goes high. A user can

also hold the

LDAC

input permanently low. In this case, the

DAC outputs update immediately after

BUSY

goes high.

Table 10.

BUSY

Pulse Width

Action

BUSY

Pulse Width (ns max)

FIFO

Enabled

FIFO

Disabled

Loading x1, c, or m to 1 channel 530 330

Loading x1, c, or m to 2 channels 700 500

Loading x1, c, or m to 3 channels 900 700

Loading x1, c, or m to 4 channels 1050 850

Loading x1, c, or m to all

40 channels

5500 5300

The value of x2 for a single channel or group of channels is

recalculated each time there is a write to any x1 register(s),

c register(s), or m register(s). During the calculation of x2,

BUSY

goes low. The duration of this

BUSY

pulse depends on

the number of channels being updated. For example, if x1, c, or

m data is written to one DAC channel,

BUSY

goes low for

550 ns (maximum). However, if data is written to two DAC

channels,

BUSY

goes low for 700 ns (maximum). As shown in

, there are approximately 200 ns of overhead due to

FIFO access.

Table 1 0

The AD5379 contains an extra feature whereby a DAC register

is not updated unless its x2 register has been written to since the

last time

LDAC

was brought low. Normally, when

LDAC

brought low, the DAC registers are filled with the contents of

the x2 registers. However the AD5379 updates the DAC register

only if the x2 data has changed, thereby removing unnecessary

digital crosstalk.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P29

AD5379ABC

Mfr. #:

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Manufacturer:

Analog Devices Inc.

Description:

Digital to Analog Converters - DAC IC 40-CH14-Bit

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AD5379ABC

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