AD5379
Rev. B | Page 6 of 28
TIMING CHARACTERISTICS
SERIAL INTERFACE
V
CC
= 2.7 V to 5.5 V; V
DD
= 11.4 V to 16.5 V; V
SS
= −11.4 V to −16.5 V; V
REF
(+) = 5 V; V
REF
(−) = −3.5 V; AGND = DGND = REFGND = 0 V;
V
BIAS
= 5 V, FIFOEN = 0 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 4.
Parameter
1, 2, 3
Limit at T
MIN
, T
MAX
Unit Description
t
1
20 ns min SCLK cycle time.
t
2
8 ns min SCLK high time.
t
3
8 ns min SCLK low time.
t
4
10 ns min
SYNC
falling edge to SCLK falling edge setup time.
t
5
4
15 ns min
24th SCLK falling edge to
SYNC
falling edge.
t
6
4
25 ns min
Minimum
SYNC
low time.
t
7
10 ns min
Minimum
SYNC
high time.
t
8
5 ns min Data setup time.
t
9
4.5 ns min Data hold time.
t
10
4, 5
30 ns max
24th SCLK falling edge to
BUSY
falling edge.
t
11
330 ns max
BUSY
pulse width low (single-channel update). See . Table 10
t
12
4
20 ns min
24th SCLK falling edge to
LDAC
falling edge.
t
13
20 ns min
LDAC
pulse width low.
t
14
150 ns typ
BUSY
rising edge to DAC output response time.
t
15
0 ns min
BUSY
rising edge to
LDAC
falling edge.
t
16
100 ns min
LDAC
falling edge to DAC output response time.
t
17
20/30 μs typ/max DAC output settling time.
t
18
10 ns min
CLR
pulse width low.
t
19
350 ns max
CLR
/
RESET
pulse activation time.
t
20
6, 7
25 ns max SCLK rising edge to sdo valid.
t
21
7
5 ns min
SCLK falling edge to
SYNC
rising edge.
t
22
7
5 ns min
SYNC
rising edge to SCLK rising edge.
t
23
7
20 ns min
SYNC
rising edge to
LDAC
falling edge.
t
24
5
30 ns min
SYNC
rising edge to
BUSY
falling edge.
t
25
10 ns min
RESET
pulse width low.
t
26
120 μs max
RESET
time indicated by
BUSY
low.
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with t
r
= t
f
= 2 ns (10% to 90% of V
CC
), and timed from a voltage level of 1.2 V.
3
See Figure 4 and Figure 5.
4
Standalone mode only.
5
This is measured with the load circuit shown in Figure 2.
6
This is measured with the load circuit shown in Figure 3.
7
Daisy-chain mode only.
TO
OUTPUT
PIN
V
CC
V
OL
C
L
50pF
R
L
2.2kΩ
03165-002
Figure 2. Load Circuit for
BUSY
Timing Diagram
2
V
OH
(min) + V
OL
(max)
200μA
200μA
I
OL
I
OH
C
L
50pF
TO
OUTPUT
PIN
03165-003
Figure 3. Load Circuit for SDO Timing Diagram
(Serial Interface, Daisy-Chain Mode)
