Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
JANUARY 1998 - REVISED JANUARY 2007
The protector characteristic off-state capacitance values are given for d.c. bias voltage, V
D
, values of -1 V, -2 V and -50 V. The TISP5150H3BJ
and TISP5190H3BJ are also given for a bias of -100 V. Values for other voltages may be determined from Figure 6. Up to 10 MHz, the
capacitance is essentially independent of frequency. Above 10 MHz, the effective capacitance is strongly dependent on connection inductance.
In Figure 12, the typical conductor bias voltages will be about -2 V and -50 V. Figure 7 shows the differential (line unbalance) capacitance
caused by biasing one protector at -2 V and the other at -50 V. For example, the TISP5070H3BJ has a differential capacitance value of 166 pF
under these conditions.
The protector should not clip or limit the voltages that occur in normal system operation. Figure 9 allows the calculation of the protector V
DRM
value at temperatures below 25 °C. The calculated value should not be less than the maximum normal system voltages. The TISP5150H3BJ,
with a V
DRM
of -120 V, can be used to protect ISDN feed voltages having maximum values of -99 V, -110 V and -115 V (range 3 through to
range 5). These three range voltages represent 0.83 (99/120), 0.92 (110/120) and 0.96 (115/120) of the -120 V TISP5150H3BJ V
DRM
. Figure 9
shows that the V
DRM
will have decreased to 0.944 of its 25 °C value at -40 °C. Thus, the supply feed voltages of -99 V (0.83) and -110 V (0.92)
will not be clipped at temperatures down to -40 °C. The -115 V (0.96) feed supply may be clipped if the ambient temperature falls below -21 °C.
Capacitance
Normal System Voltage Levels
JESD51 Thermal Measurement Method
To standardize thermal measurements, the EIA (Electronic Industries Alliance) has created the JESD51 standard. Part 2 of the standard
(JESD51-2, 1995) describes the test environment. This is a 0.0283 m
3
(1 ft
3
) cube which contains the test PCB (Printed Circuit Board)
horizontally mounted at the center. Part 3 of the standard (JESD51-3, 1996) defines two test PCBs for surface mount components; one for
packages smaller than 27 mm on a side and the other for packages up to 48 mm. The SMB (DO-214AA) measurements used the smaller 76.2
mm x 114.3 mm (3.0 ” x 4.5 ”) PCB. The JESD51-3 PCBs are designed to have low effective thermal conductivity (high thermal resistance) and
represent a worse case condition. The PCBs used in the majority of applications will achieve lower values of thermal resistance and so can
dissipate higher power levels than indicated by the JESD51 values.
TISP5xxxH3BJ Overvoltage Protection Series
APPLICATIONS INFORMATION
The protector can withstand currents applied for times not exceeding those shown in Figure 8. Currents that exceed these times must be
terminated or reduced to avoid protector failure. Fuses, PTC (Positive Temperature Coefficient) resistors and fusible resistors are overcurrent
protection devices which can be used to reduce the current flow. Protective fuses may range from a few hundred milliamperes to one ampere.
In some cases it may be necessary to add some extra series resistance to prevent the fuse opening during impulse testing. The current versus
time characteristic of the overcurrent protector must be below the line shown in Figure 8. In some cases there may be a further time limit
imposed by the test standard (e.g. UL 1459 wiring simulator failure).
AC Power Testing
“TISP” is a trademark of Bourns, Ltd., a Bourns Company, and is Registered in U.S. Patent and Trademark Office.
“Bourns” is a registered trademark of Bourns, Inc. in the U.S. and other countries.
