8
Register Read (I
2
C
TM
Read)
S
Slave Addr
7 Bit
0A
Address
8 Bit
AS
Slave Addr
7 Bit
1A
Data
8 Bit
NP
S
Slave Addr
7 Bit
0A
Address
8 Bit
AS
Slave Addr
7 Bit
1A
Data
8-Bit
A
Data
8-Bit
A…
Data
8-Bit
NP
From Master to Slave
From Slave to Master
S
P
A
N
Start Condition
Stop Condition
Acknowledge (ACK)
Not Acknowledge (NACK)
ReadWrite
ReadWrite
Register Block Read (I
2
C
TM
Read)
I
2
C Protocol
Interface and control of the APDS-9306/APDS-9306-065 is
accomplished through an I
2
C serial compatible interface
(standard or fast mode) to a set of registers that provide
access to device control functions and output data. The
device supports a single slave address of 0X52 hex using
7-bit addressing protocol. (Contact factory for other ad-
dressing options).
I²C Register Read
The registers can be read individually or in block read
mode. When two or more bytes are read in block read
mode, reserved register addresses are skipped and the
next valid address is referenced. If the last valid address
has been reached, but the master continues with the
block read, the address counter in the device will not roll
over and the device returns 00HEX for every subsequent
byte read.
The block read operation is the only way to ensure correct
data read out of multi-byte registers and to avoid splitting
of results with HIGH and LOW bytes originating from
di erent conversions. During block read access on ALS
result registers, the result update is blocked.
If a read access is started on an address belonging to a
non-readable register, the APDS-9306/APDS-9306-065
will re-turn NACK until the I
2
C™ operation is ended.
Read operations must follow the Register Read timing
diagram as below.
I²C Register Write
The APDS-9306/APDS-9306-065 registers can be written
to individually or in block write mode. When two or more
bytes are written in block write mode, reserved registers
and read-only registers are skipped. The transmitted data
is automatically applied to the next writable register. If
a register includes read (R) and read/write (RW) bits, the
register is not skipped. Data written to read-only bits are
ignored.
If the last valid address of the APDS-9306/APDS-9306-
065 address range is reached but the master attempts to
continue the block write operation, the address counter
of the APDS-9306/APDS-9306-065 will not roll over. The
APDS-9306/APDS-9306-065 will return NACK for every
following byte sent by the master until the I
2
C™ operation
is ended.
If a write access is started on an address belonging to a
non-writeable register, the APDS-9306/APDS-9306-065
will return NACK until the I
2
C™ operation is ended.
Write operations must follow the Register Write timing
diagram below.
S
Slave Addr
7 Bit
0 A Address A
Data
8-Bit
AP
S
Slave Addr
7 Bit
0 A Address A
Data
8-Bit
A
Data
8-Bit
A…
Data
8-Bit
AP
Write
Write
Register Write (I
2
C
TM
Write)
Register Block Write (I
2
C
TM
Write)
From Master to Slave
From Slave to Master
S
P
A
N
Start Condition
Stop Condition
Acknowledge (ACK)
Not Acknowledge (NACK)
