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ISL6532CCRZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
10
Had the cause of the over current still been present after the
delay interval, the over current condition would be sensed
and the regulator would be shut down again for another
delay interval of three soft start cycles. The resulting hiccup
mode style of protection would continue to repeat indefinitely.
The over-current function will trip at a peak inductor current
(I
PEAK)
determined by:
where I
OCSET
is the internal OCSET current source (20A
typical). The OC trip point varies mainly due to the MOSFET
r
DS(ON)
variations. To avoid over-current tripping in the
normal operating load range, find the R
OCSET
resistor from
the equation above with:
1. The maximum r
DS(ON)
at the highest junction
temperature.
2. The minimum I
OCSET
from the specification table.
3. Determine I
PEAK
for:
, whereI is
the output inductor ripple current.
For an equation for the ripple current see the section under
component guidelines titled ‘Output Inductor Selection’.
A small ceramic capacitor should be placed in parallel with
R
OCSET
to smooth the voltage across
R
OCSET
in the
presence of switching noise on the input voltage.
V
TT
Over Current Protection
The internal V
TT
LDO is protected from fault conditions
through a 3.3A current limit. This current limit protects the
ISL6532C if the LDO is sinking or sourcing current. During
an overcurrent event on the V
TT
LDO, only the V
TT
LDO is
disabled. Once the over current condition on the V
TT
rail is
removed, V
TT
will recover.
Over/Under Voltage Protection
All three regulators are protected from faults through internal
Over/Under voltage detection circuitry. If the any rail falls
below 85% of the targeted voltage, then an undervoltage
event is tripped. An under voltage will disable all three
regulators for a period of 3 soft-start cycles, after which a
normal soft-start is initiated. If the output is still under 85% of
target, the regulators will continue to be disabled and soft-
started in a hiccup mode until the fault is cleared. This
protection feature works much the same as the VDDQ PWM
over current protection works. See Figure 3.
If the any rail exceeds 115% of the targeted voltage, then all
three outputs are immediately disabled. The ISL6532C will
not re-enable the outputs until either the bias voltage is
toggled in order to initiate a POR or the S5 signal is forced
LOW and then back to HIGH.
Thermal Protection (S0/S3 State)
If the ISL6532C IC junction temperature reaches a nominal
temperature of 140
o
C, all regulators will be disabled. The
ISL6532C will not re-enable the outputs until the junction
temperature drops below 110
o
C and either the bias voltage
is toggled in order to initiate a POR or the SLP_S5 signal is
forced LOW and then back to HIGH.
Shoot-Through Protection
A shoot-through condition occurs when both the upper and
lower MOSFETs are turned on simultaneously, effectively
shorting the input voltage to ground. To protect from a shoot-
through condition, the ISL6532C incorporates specialized
circuitry which insures that complementary MOSFETs are
not ON simultaneously.
The adaptive shoot-through protection utilized by the V
DDQ
regulator looks at the lower gate drive pin, LGATE, and the
upper gate drive pin, UGATE, to determine whether a
MOSFET is ON or OFF. If the voltage from UGATE or from
LGATE to GND is less than 0.8V, then the respective
MOSFET is defined as being OFF and the other MOSFET is
allowed to turned ON. This method allows the V
DDQ
regulator to both source and sink current.
Since the voltage of the MOSFET gates are being measured
to determine the state of the MOSFET, the designer is
encouraged to consider the repercussions of introducing
external components between the gate drivers and their
respective MOSFET gates before actually implementing
such measures. Doing so may interfere with the shoot-
through protection.
TIME
T1
T0 T2
500mV/DIV
V
DDQ
V
AGP
V
TT
FIGURE 3. V
DDQ
and V
TT
OVER CURRENT PROTECTION
AND V
TT
/V
AGP
LDO UNDER VOLTAGE
PROTECTION RESPONSES
INTERNAL SOFT-START FUNCTION
DELAY INTERVAL
I
PEAK
I
OCSET
x R
OCSET
r
DS ON
-----------------------------------------------------=
I
PEAK
I
OUT MAX
I
2
----------
+>
ISL6532C
11
Application Guidelines
Layout Considerations
Layout is very important in high frequency switching
converter design. With power devices switching efficiently at
250kHz, the resulting current transitions from one device to
another cause voltage spikes across the interconnecting
impedances and parasitic circuit elements. These voltage
spikes can degrade efficiency, radiate noise into the circuit,
and lead to device over-voltage stress. Careful component
layout and printed circuit board design minimizes these
voltage spikes.
As an example, consider the turn-off transition of the control
MOSFET. Prior to turn-off, the MOSFET is carrying the full
load current. During turn-off, current stops flowing in the
MOSFET and is picked up by the lower MOSFET. Any
parasitic inductance in the switched current path generates a
large voltage spike during the switching interval. Careful
component selection, tight layout of the critical components,
and short, wide traces minimizes the magnitude of voltage
spikes.
There are two sets of critical components in the ISL6532C
switching converter. The switching components are the most
critical because they switch large amounts of energy, and
therefore tend to generate large amounts of noise. Next are
the small signal components which connect to sensitive
nodes or supply critical bypass current and signal coupling.
A multi-layer printed circuit board is recommended. Figure 4
shows the connections of the critical components in the
converter. Note that capacitors C
IN
and C
OUT
could each
represent numerous physical capacitors. Dedicate one solid
layer, usually a middle layer of the PC board, for a ground
plane and make all critical component ground connections
with vias to this layer. Dedicate another solid layer as a
power plane and break this plane into smaller islands of
common voltage levels. Keep the metal runs from the
PHASE terminals to the output inductor short. The power
plane should support the input power and output power
nodes. Use copper filled polygons on the top and bottom
circuit layers for the phase nodes. Use the remaining printed
circuit layers for small signal wiring. The wiring traces from
the GATE pins to the MOSFET gates should be kept short
and wide enough to easily handle the 1A of drive current.
In order to dissipate heat generated by the internal V
TT
LDO, the ground pad, pin 29, should be connected to the
internal ground plane through at least four vias. This allows
the heat to move away from the IC and also ties the pad to
the ground plane through a low impedance path.
The switching components should be placed close to the
ISL6532C first. Minimize the length of the connections
between the input capacitors, C
IN
, and the power switches
by placing them nearby. Position both the ceramic and bulk
input capacitors as close to the upper MOSFET drain as
possible. Position the output inductor and output capacitors
between the upper and lower MOSFETs and the load.
The critical small signal components include any bypass
capacitors, feedback components, and compensation
components. Place the PWM converter compensation
components close to the FB and COMP pins. The feedback
resistors should be located as close as possible to the FB
pin with vias tied straight to the ground plane as required.
Feedback Compensation - PWM Buck Converter
Figure 5 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V
OUT
) is regulated to the Reference voltage level. The error
amplifier output (V
E/A
) is compared with the oscillator (OSC)
triangular wave to provide a pulse-width modulated (PWM)
wave with an amplitude of V
IN
at the PHASE node.
V
DDQ
5VSBY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
L
OUT
C
OUT1
C
IN
V
IN_DDR
KEY
COMP
ISL6532C
UGATE
R
4
R
2
C
BP
FB
DRIVE2
GNDP
5VSBY
FIGURE 4. PRINTED CIRCUIT BOARD POWER PLANES
AND ISLANDS
R
1
V
AGP
FB2
C
2
VIA CONNECTION TO GROUND PLANE
C
OUT3
LOAD
LOAD
Q
1
V
IN_AGP
R
5
R
6
PHASE
R
3
C
3
C
1
Q
2
12V
ATX
C
BP
GNDP
P12V
Q
3
LGATE
P5VSBY
VDDQ(3)
VTT(2)
C
OUT2
LOAD
V
DDQ
V
TT
NCH
GND PAD
ISL6532C
12
The PWM wave is smoothed by the output filter (L
O
and
C
O
).
The modulator transfer function is the small-signal transfer
function of V
OUT
/V
E/A
. This function is dominated by a DC
Gain and the output filter (L
O
and C
O
), with a double pole
break frequency at F
LC
and a zero at F
ESR
. The DC Gain of
the modulator is simply the input voltage (V
IN
) divided by the
peak-to-peak oscillator voltage V
OSC
.
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the ISL6532C) and the impedance networks Z
IN
and Z
FB
. The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f
0dB
) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f
0dB
and
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R
1
, R
2
,
R
3
, C
1
, C
2
, and C
3
) in Figure 5. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick Gain (R
2
/R
1
) for desired converter bandwidth.
2. Place 1
ST
Zero Below Filter’s Double Pole (~75% F
LC
).
3. Place 2
ND
Zero at Filter’s Double Pole.
4. Place 1
ST
Pole at the ESR Zero.
5. Place 2
ND
Pole at Half the Switching Frequency.
6. Check Gain against Error Amplifier’s Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
Compensation Break Frequency Equations
Figure 6 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual Modulator Gain has a high
gain peak due to the high Q factor of the output filter and is
not shown in Figure 6. Using the above guidelines should
give a Compensation Gain similar to the curve plotted. The
open loop error amplifier gain bounds the compensation
gain. Check the compensation gain at F
P2
with the
capabilities of the error amplifier. The Closed Loop Gain is
constructed on the graph of Figure 6 by adding the
Modulator Gain (in dB) to the Compensation Gain (in dB).
This is equivalent to multiplying the modulator transfer
function to the compensation transfer function and plotting
the gain.
The compensation gain uses external impedance networks
Z
FB
and Z
IN
to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
Feedback Compensation - AGP LDO Controller
Figure 7 shows the AGP LDO power and control stage. This
LDO, which uses a MOSFET as the linear pass element,
requires feedback compensation to insure stability of the
system. The LDO requires compensation because of the
output impedance of the error amplifier.
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN AND OUTPUT
VOLTAGE SELECTION
V
DDQ
REFERENCE
L
O
C
O
ESR
V
IN
V
OSC
ERROR
AMP
PWM
DRIVER
(PARASITIC)
Z
FB
+
-
REFERENCE
R
1
R
3
R
2
C
3
C
1
C
2
COMP
V
DDQ
FB
Z
FB
ISL6532C
Z
IN
COMPARATOR
DRIVER
DETAILED COMPENSATION COMPONENTS
PHASE
V
E/A
+
-
+
-
Z
IN
OSC
R
4
V
DDQ
0.8 1
R
1
R
4
-------+



=
F
LC
1
2 x L
O
x C
O
-------------------------------------------= F
ESR
1
2 x ESR x C
O
--------------------------------------------=
F
Z1
1
2 x R
2
x C
2
------------------------------------=
F
Z2
1
2 x R
1
R
3
+ x C
3
-------------------------------------------------------=
F
P1
1
2 x R
2
x
C
1
x C
2
C
1
C
2
+
----------------------



---------------------------------------------------------=
F
P2
1
2 x R
3
x C
3
------------------------------------=
100
80
60
40
20
0
-20
-40
-60
F
P1
F
Z2
10M1M100K10K1K10010
OPEN LOOP
ERROR AMP GAIN
F
Z1
F
P2
20LOG
F
LC
F
ESR
COMPENSATION
GAIN (dB)
FREQUENCY (Hz)
GAIN
20LOG
(V
IN
/V
OSC
)
MODULATOR
GAIN
(R
2
/R
1
)
FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
CLOSED LOOP
GAIN
ISL6532C
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

ISL6532CCRZ

Mfr. #:
Buy ISL6532CCRZ
Manufacturer:
Renesas / Intersil
Description:
Switching Controllers 3-IN-1 DDRG W/3ALDO SPRINGDALE MBS 28L
Lifecycle:
New from this manufacturer.
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