ISL6532CCRZ Datasheet ISL6532CCRZ-T, ISL6532CCRZ, ISL6532CCR | P7-P9

Functional Pin Description

5VSBY (Pin 2)

5VSBY is the bias supply of the ISL6532C. It is typically

connected to the 5V standby rail of an ATX power supply.

During S4/S5 sleep states the ISL6532C enters a reduced

power mode and draws less than 1mA (I

CC_S5

) from the

5VSBY supply. The supply to 5VSBY should be locally

bypassed using a 0.1F capacitor.

P12V (Pin 25)

P12V provides the gate drive to the switching MOSFETs of

the PWM power stage. The V

regulation circuit and the

Linear Driver are also powered by P12V. P12V is not

required except during S0/S1/S2 operation. P12V is typically

connected to the +12V rail of an ATX power supply.

5VSBY (Pin 11)

This pin provides the V

DDQ

output power during S3 sleep

state. The regulator is capable of providing standby V

DDQ

power from either the 5VSBY or 3.3VSBY rail. It is

recommended that the 5VSBY rail be used as the output

current handling capability of the standby LDO is higher than

with the 3.3VSBY rail.

GND, GNDA, GNDP, GNDQ (Pins 1, 3, 4, 17, 29)

The GND terminals of the ISL6532C provide the return path

for the V

LDO, standby LDO and switching MOSFET gate

drivers. High ground currents are conducted directly through

the exposed paddle of the QFN package which must be

electrically connected to the ground plane through a path as

low in inductance as possible. GNDA is the Analog ground

pin, GNDQ is the return for the VTT regulator and GNDP is

the return for the upper and lower gate drives.

UGATE (Pin 26)

UGATE drives the upper (control) FET of the V

DDQ

synchronous buck switching regulator. UGATE is driven

between GND and P12V.

LGATE (Pin 27)

LGATE drives the lower (synchronous) FET of the V

DDQ

synchronous buck switching regulator. LGATE is driven

between GND and P12V.

FB (Pin 15) and COMP (Pin 16)

The V

DDQ

switching regulator employs a single voltage

control loop. FB is the negative input to the voltage loop error

amplifier. The positive input of the error amplifier is

connected to a precision 0.8V reference and the output of

the error amplifier is connected to the COMP pin. The V

DDQ

output voltage is set by an external resistor divider

connected to FB. With a properly selected divider, V

DDQ

can

be set to any voltage between the power rail (reduced by

converter losses) and the 0.8V reference. Loop

compensation is achieved by connecting an AC network

across COMP and FB.

The FB pin is also monitored for under and over-voltage

events.

PHASE (Pin 20)

Connect this pin to the upper MOSFET’s source. This pin is

used to monitor the voltage drop across the upper MOSFET

for over-current protection.

OCSET (Pin 12)

Connect a resistor (R

OCSET

) from this pin to the drain of the

upper MOSFET. R

OCSET

, an internal 20A current source

OCSET

), and the upper MOSFET on-resistance (r

DS(ON)

)

set the converter over-current (OC) trip point according to

the following equation:

An over-current trip cycles the soft-start function.

VDDQ (Pins 7, 8, 9)

The VDDQ pins should be connected externally together to

the regulated V

DDQ

output. During S0/S1 states, the VDDQ

pins serve as inputs to the V

regulator and to the V

Reference precision divider. During S3 state, the VDDQ pins

serve as an output from the integrated standby LDO.

VTT (Pins 5, 6)

The VTT pins should be connect externally together. During

S0/S1 states, the VTT pins serve as the outputs of the V

linear regulator. During S3 state, the V

regulator is

disabled.

VTTSNS (Pin 10)

VTTSNS is used as the feedback for control of the V

linear

regulator. Connect this pin to the V

output at the physical

point of desired regulation.

VREF_OUT (Pin 13)

VREF_OUT is a buffered version of V

and also acts as the

reference voltage for the V

linear regulator. It is

recommended that a minimum capacitance of 0.1F is

connected between V

DDQ

and VREF_OUT and also

between VREF_OUT and ground for proper operation.

VREF_IN (Pin 14)

A capacitor, C

, connected between VREF_IN and ground

is required. This capacitor and the parallel combination of

the Upper and Lower Divider Impedance (R

||R

), sets the

time constant for the start up ramp when transitioning from

S3 to S0/S1/S2.

The minimum value for C

can be found through the

following equation:

The calculated capacitance, C

, will charge the output

capacitor bank on the V

rail in a controlled manner without

reaching the current limit of the V

LDO.

PEAK

OCSET

DS ON

-------------------------------------------------=

VTTOUT

DDQ



10 2A R





------------------------------------------------

ISL6532C

NCH (Pin 22)

NCH is an open-drain output that controls the MOSFET

blocking backfeed from V

DDQ

to the input rail during sleep

states. A 2k or larger resistor is to be tied between the 12V

rail and the NCH pin. Until the voltage on the NCH pin

reaches the NCH trip level, the PWM is disabled.

If NCH is not actively utilized, it still must be tied to the 12V

rail through a resistor. For systems using 5V dual as the

input to the switching regulator, a time constant, in the form

of a capacitor, can be added to the NCH pad to delay start of

the PWM switcher until the 5V dual has switched from

5VSBY to 5VATX.

PGOOD (Pin 21)

Power Good is an open-drain logic output that changes to a

logic low if any of the three regulators are out of regulation in

S0/S1/S2 state. PGOOD will always be low in any state

other than S0/S1/S2.

SLP_S5# (Pin 24)

This pin accepts the SLP_S5# sleep state signal.

SLP_S3# (Pin 23)

This pin accepts the SLP_S3# sleep state signal.

FB2 (Pin 18)

Connect the output of the external linear regulator to this pin

through a properly sized resistor divider. The voltage at this

pin is regulated to 0.8V. This pin is monitored for under and

over-voltage events.

DRIVE2 (Pin 19)

Connect this pin to the gate terminal of an external N-

Channel MOSFET transistor. This pin provides the gate

voltage for the linear regulator pass transistor. It also

provides a means of compensating the error amplifier for

applications requiring the transient response of the linear

regulator to be optimized.

Functional Description

Overview

The ISL6532C provides complete control, drive, protection

and ACPI compliance for a regulator powering DDR memory

systems. It is primarily designed for computer applications

powered from an ATX power supply. A 250kHz Synchronous

Buck Regulator with a precision 0.8V reference provides the

proper Core voltage to the system memory of the computer.

An internal LDO regulator with the ability to both sink and

source current and an externally available buffered

reference that tracks the V

DDQ

output by 50% provides the

termination voltage. The ISL6532C also features an

LDO regulator for 1.5V AGP Video and Core voltage.

ACPI compliance is realized through the SLP_S3 and

SLP_S5 sleep signals and through monitoring of the 12V

ATX bus.

Initialization

The ISL6532C automatically initializes upon receipt of input

power. Special sequencing of the input supplies is not

necessary. The Power-On Reset (POR) function continually

monitors the input bias supply voltages. The POR monitors

the bias voltage at the 5VSBY and P12V pins. The POR

function initiates soft-start operation after the bias supply

voltages exceed their POR thresholds.

ACPI State Transitions

Cold Start (S4/S5 to S0 Transition)

At the onset of a mechanical start, the ISL6532C receives its

bias voltage from the 5V Standby bus (5VSBY). As soon as

the SLP_S3 and SLP_S5 have transitioned HIGH, the

ISL6532C starts an internal counter. Following a cold start or

any subsequent S4/S5 state, state transitions are ignored

until the system enters S0/S1. None of the regulators will

begin the soft start procedure until the 5V Standby bus has

exceeded POR, the 12V bus has exceeded POR and V

NCH

has exceeded the trip level.

Once all of these conditions are met, the PWM error

amplifier will first be reset by internally shorting the COMP

pin to the FB pin. This reset lasts for 2048 clock cycles,

which is typically 8.2ms (one clock cycle = 1/f

OSC

). The

digital soft start sequence will then begin.

The PWM error amplifier reference input is clamped to a

level proportional to the soft-start voltage. As the soft-start

voltage slews up, the PWM comparator generates PHASE

pulses of increasing width that charge the output

capacitor(s). The internal VTT LDO will also soft start

through the reference that tracks the output of the PWM

regulator. The reference for the AGP LDO controller will rise

relative to the soft start reference. The soft start lasts for

2048 clock cycles, which is typically 8.2ms. This method

provides a rapid and controlled output voltage rise.

FIGURE 1. TYPICAL COLD START

DDQ

12VATX 2V/DIV

5VSBY

1V/DIV

500mV/DIV

AGP

500mV/DIV

12V POR

SOFT START

INITIATES

SOFT START ENDS

PGOOD COMPARATOR

ENABLED

2048 CLOCK

CYCLES

2048 CLOCK

CYCLES

PGOOD

5V/DIV

ISL6532C

Figure 1 shows the soft start sequence for a typical cold

start. Due to the soft start capacitance, C

, on the

VREF_IN pin, the S5 to S0 transition profile of the V

rail

will have a more rounded features at the start and end of the

soft start whereas the V

DDQ

profile has distinct starting and

ending points to the ramp up.

By directly monitoring 12VATX and the SLP_S3 and SLP_S5

signals the ISL6532C can achieve PGOOD status

significantly faster than other devices that depend on

Latched_Backfeed_Cut for timing.

Active to Sleep (S0 to S3 Transition)

When SLP_S3 goes LOW with SLP_S5 still HIGH, the

ISL6532C will disable the V

linear regulator and the AGP

LDO controller. The V

DDQ

standby regulator will be enabled

and the V

DDQ

switching regulator will be disabled. NCH is

pulled low to disable the backfeed blocking MOSFET.

PGOOD will also transition LOW. When V

is disabled, the

internal reference for the V

regulator is internally shorted

to the V

rail. This allows the V

rail to float. When

floating, the voltage on the V

rail will depend on the

leakage characteristics of the memory and MCH I/O pins. It

is important to note that the V

rail may not bleed down to 0V.

The V

DDQ

rail will be supported in the S3 state through the

standby V

DDQ

LDO. When S3 transitions LOW, the Standby

regulator is immediately enabled. The switching regulator is

disabled synchronous to the switching waveform. The shut

off time will range between 4 and 8s. The standby LDO is

capable of supporting up to 650mA of load with P5VSBY tied

to the 5V Standby Rail. The standby LDO may receive input

from either the 3.3V Standby rail or the 5V Standby rail

through the P5VSBY pin. It is recommended that the 5V

Standby rail be used as the current delivery capability of the

LDO is greater.

Sleep to Active (S3 to S0 Transition)

When SLP_S3 transitions from LOW to HIGH with SLP_S5

held HIGH and after the 12V rail exceeds POR, the

ISL6532C will enable the V

DDQ

switching regulator, disable

the V

DDQ

standby regulator, enable the V

LDO and force

the NCH pin to a high impedance state turning on the

blocking MOSFET. The AGP LDO goes through a 2048

clock cycle soft-start. The internal short between the V

reference and the V

rail is released. Upon release of the

short, the capacitor on VREF_IN is then charged up through

the internal resistor divider network. The V

output will

follow this capacitor charge up, and acting as the S3 to S0

transition soft start for the V

rail. The PGOOD comparator

is enabled only after 2048 clock cycles, or typically 8.2ms,

have passed following the S3 transition to a HIGH state.

Figure 2 illustrates a typical state transition from S3 to S0. It

should be noted that the soft start profile of the V

LDO

output will vary according to the value of the capacitor on the

VREF_IN pin.

Active to Shutdown (S0 to S5 Transition)

When the system transitions from active, S0, state to

shutdown, S4/S5, state, the ISL6532C IC disables all

regulators and forces the PGOOD pin and the NCH pin LOW.

DDQ

Over Current Protection (S0 State)

The over-current function protects the switching converter

from a shorted output by using the upper MOSFET on-

resistance, r

DS(ON)

, to monitor the current. This method

enhances the converter’s efficiency and reduces cost by

eliminating a current sensing resistor.

The over-current function cycles the soft-start function in a

hiccup mode to provide fault protection. A resistor (R

OCSET

)

programs the over-current trip level (see Typical Application

diagrams on pages 3 and 4). An internal 20A (typical)

current sink develops a voltage across R

OCSET

that is

referenced to the converter input voltage. When the voltage

across the upper MOSFET (also referenced to the converter

input voltage) exceeds the voltage across R

OCSET

, the over-

current function initiates a soft-start sequence. The initiation

of soft start will affect all regulators. The V

regulator is

directly affected as it receives it’s reference from V

DDQ

. The

AGP LDO will also be soft started, and as such, the AGP

LDO voltage will be disabled while the V

DDQ

regulator is

disabled.

Figure 3 illustrates the protection feature responding to an

over current event. At time T0, an over current condition is

sensed across the upper MOSFET. As a result, the regulator

is quickly shutdown and the internal soft-start function begins

producing soft-start ramps. The delay interval seen by the

output is equivalent to three soft-start cycles. The fourth

internal soft-start cycle initiates a normal soft-start ramp of

the output, at time T1. The output is brought back into

regulation by time T2, as long as the over current event has

cleared.

FIGURE 2. TYPICAL S3 TO S0 STATE TRANSITION

DDQ

12VATX 2V/DIV

500mV/DIV

PGOOD

5V/DIV

AGP

500mV/DIV

TT_FLOAT

12V POR PGOOD COMPARATOR

ENABLED

2048 CLOCK

CYCLES

ISL6532C

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P16

ISL6532CCRZ

Mfr. #:

Buy ISL6532CCRZ

Manufacturer:

Renesas / Intersil

Description:

Switching Controllers 3-IN-1 DDRG W/3ALDO SPRINGDALE MBS 28L

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ISL6532CCRZ

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