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NB3N121KMNG

P1-P3P4-P6P7-P9P10-P11
NB3N121K
http://onsemi.com
7
Figure 3. AC Reference Measurement
CLK
CLK
Q
x
Q
x
t
P
LH t
P
HL
V
INPP
= V
IH
(CLK) − V
IL
(CLK)
= V
IH
(CLK) − V
IL
(CLK)
V
OUTPP
= V
OH
(Q
x
) − V
OL
(Q)
x
= V
OH
(Q
x
) − V
OL
(Q
x
)
Dt
P
LH Dt
P
HL
t
r
t
f
525 mV
175 mV
525 mV
175 mV
tr
MAX
− tr
MIN
= Dt
r
tr
MIN
tf
MAX
− tf
MIN
= Dt
f
tf
MIN
tf
MAX
tr
MAX
DV
CROSS
V
CROSS
(a) Propagation Delay and Propagation
Delay Variation
(b) tr, tf and Dtr, Dtf
(c) VCROSS and DVCROSS
Q
X
Q
x
Q
x
Q
X
Figure 4. Single−Ended Interconnect V
th
Reference Voltage
CLK
V
th
CLK
V
th
Figure 5. V
th
Diagram
V
CC
V
EE
V
CMRmin
V
CMRmax
V
CMR
IN
IN
V
IHDmax
V
ILDmax
V
ID
= V
IHD
− V
ILD
V
IHDtyp
V
ILDtyp
V
IHDmin
V
ILDmin
NB3N121K
http://onsemi.com
8
Figure 6. Typical Termination Configuration for Output Driver and Device Evaluation
A. Connect 475 W resistor RREF from IREF pin to GND.
B. R
S1
, R
S2
: 0 W for Test and Evaluation. Select to Minimizing Ringing.
C. C
L1
, C
L2
: Receiver Input Simulation (for test only not added to application circuit.
D. R
L1
, R
L2
Termination and Load Resistors Located at Receiver Inputs.
C
L1
C
2 pF
C
L2
C
2 pF
Z
0
= 50 W
Z
0
= 50 W
Receiver
R
S1
B
R
S2
B
NB3N121K
Driver
RREF
A
R
L1
D
50 W
R
L2
D
50 W
Qx
Qx
50 W*
V
TCLK
= V
TCLK
= V
CC
− 2.0 V
LVPECL
Driver
Z
0
= 50 W
Z
0
= 50 W
V
CC
= 3.3 V / 2.5 V V
CC
= 3.3 V
GND GND
50 W*
V
TCLK
V
TCLK
Figure 7. LVPECL Interface
*RTIN, Internal Input Termination Resistor
50 W*
V
TCLK
= V
TCLK
LVDS
Driver
Z
0
= 50 W
Z
0
= 50 W
V
CC
= 3.3 V / 2.5 V / 1.8 V V
CC
= 3.3 V
GND GND
50 W*
V
TCLK
V
TCLK
Figure 8. LVDS Interface
*RTIN, Internal Input Termination Resistor
NB3N121K NB3N121K
CLK
CLK
CLK
CLK
NB3N121K
http://onsemi.com
9
50 W*
V
TCLK
= V
TCLK
= GND
HCSL
Driver
Z
0
= 50 W
Z
0
= 50 W
V
CC
= 3.3 V
GND GND
50 W*
V
TCLK
V
TCLK
Figure 9. Standard 50 W Load HCSL Interface
*RTIN, Internal Input Termination Resistor
NB3N121K
GND
50 W*
V
TCLK
= OPEN
LVCMOS/
LVTTL
Driver
Z
0
= 50 W
V
CC
= 3.3 V / 2.5 V / 1.8 V V
CC
= 3.3 V
GND GND
50 W*
V
TCLK
V
TCLK
*RTIN, Internal Input Termination Resistor
NB3N121K
Figure 10. LVCMOS/LVTTL Interface
CLK = V
th
V
th
V
TCLK
= OPEN
CLK
CLK
V
CC
= 3.3 V / 2.5 V / 1.8 V
CLK
CLK
Figure 11. HCSL Interface Termination to LVDS
NB3N121K
Device
LVDS
Device
Qx
Qx
Z
o
= 50 W
Z
o
= 50 W
R
L
= 150 W R
L
= 150 W
100 W 100 W
R
REF
IREF
Figure 12. Simplified HCSL Output Structure
R
REF
R
L1
R
L2
Qx QxIREF
2.63 mA
475 W 50 W 50 W
14.2 mA
P1-P3P4-P6P7-P9P10-P11

NB3N121KMNG

Mfr. #:
Buy NB3N121KMNG
Manufacturer:
ON Semiconductor
Description:
Clock Buffer 3.3V 1:21 DIFF FANOUT CLO
Lifecycle:
New from this manufacturer.
Delivery:
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