ML610Q178 REFERENCE BOARD Datasheet ML610Q178-NNNGAZ0AAL, ML610Q178 REFERENCE BOARD | P10-P12

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Primary function Secondary function Tertiary function Fourthly function

No.

name

I/O Description

name

I/O Description

name

I/O Description

name

I/O Description

58 PE3 I/O Input/output port SEG27 O

LCD

segment

⎯ ⎯ ⎯ ⎯ ⎯ ⎯

59 PE4 I/O Input/output port SEG28 O

LCD

segment

⎯ ⎯ ⎯ ⎯ ⎯ ⎯

60 PE5 I/O Input/output port SEG29 O

LCD

segment

⎯ ⎯ ⎯ ⎯ ⎯ ⎯

61 PE6 I/O Input/output port SEG30 O

LCD

segment

⎯ ⎯ ⎯ ⎯ ⎯ ⎯

62 PE7 I/O Input/output port SEG31 O

LCD

segment

⎯ ⎯ ⎯ ⎯ ⎯ ⎯

63 PF0 I/O Input/output port SEG32 O

LCD

segment

⎯ ⎯ ⎯ ⎯ ⎯ ⎯

64 PF1 I/O Input/output port SEG33 O

LCD

segment

⎯ ⎯ ⎯ ⎯ ⎯ ⎯

65 PF2 I/O Input/output port SEG34 O

LCD

segment

⎯ ⎯ ⎯ ⎯ ⎯ ⎯

66 PF3 I/O Input/output port SEG35 O

LCD

segment

⎯ ⎯ ⎯ ⎯ ⎯ ⎯

67 PF4 I/O Input/output port SEG36 O

LCD

segment

⎯ ⎯ ⎯ ⎯ ⎯ ⎯

68 PF5 I/O Input/output port SEG37 O

LCD

segment

⎯ ⎯ ⎯ ⎯ ⎯ ⎯

69 PF6 I/O Input/output port SEG38 O

LCD

segment

⎯ ⎯ ⎯ ⎯ ⎯ ⎯

70 PF7 I/O Input/output port SEG39 O

LCD

segment

⎯ ⎯ ⎯ ⎯ ⎯ ⎯

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PIN DESCRIPTION

Pin name I/O Description

Primary/

Secondary

Logic

Power supply

—

Negative power supply pin

— —

—

Positive power supply pin

— —

DDL

—

Positive power supply pin for internal logic (internally generated). Connect

capacitors (C

) (see Measuring Circuit 1) between this pin and V

— —

—

Power supply pin for programming Flash ROM.

— —

—

Power supply pins for LCD bias (external input)

— —

—

Power supply pins for LCD bias (external input)

— —

—

Power supply pins for LCD bias (external input)

— —

Test

TEST0

I/O

Input/output pin for testing. Has a pull-down resistor built in.

— Positive

TEST1_N

I/O

Input/output pin for testing. Has a pull-up resistor built in.

— Negative

System

RESET_N I

Reset input pin. When this pin is set to a “L” level, the device is placed in

system reset mode and the internal circuit is initialized. If after that this pin

is set to a “H” level, program execution starts. This pin has a pull-up

resistor built in.

— Negative

XT0 I — —

XT1 O

Crystal connection pin for low-speed clock. A 32.768 kHz crystal oscillator

(see measuring circuit 1) is connected to this pin. Capacitors C

and C

are connected across this pin and V

as required.

— —

OSC0 I Secondary —

OSC1 O

External input pin for high-speed clock. This function is allocated to the

secondary function of the P10 pin.

Secondary —

LSCLK O

Low-speed clock output. This function is allocated to the secondary function

of the P20/P36 pin.

Secondary —

OUTCLK O

High-speed clock output. This function is allocated to the secondary

function of the P21 pin.

Secondary —

General-purpose input port

P00 to P03 I

P10 to P11 I

General-purpose input ports. Provided with a secondary function for each

port. Cannot be used as ports if their secondary functions are used.

Primary Positive

General-output input port

P20 to P23 O

General-purpose output ports.Provided with a secondary function for each

port. Cannot be used as ports if their secondary functions are used.

Primary Positive

P90 to P93 O

General-purpose output ports.Provided with a secondary function for each

port. Cannot be used as ports if their secondary functions are used.

Primary Positive

General-purpose input/output port

P30 to P36

P40 to P47

P50 to P53

General-purpose input/output ports.Provided with a secondary function for

each port. Cannot be used as ports if their secondary functions are used.

PC0 to PC7

PD0 to PD7

PE0 to PE7

PF0 to PF7

I/O

General-purpose input/output ports.Provided with a LCD segment for each

port. Cannot be used as ports if LCD segment are used.

Primary Positive

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Pin name I/O Description

Primary/

Secondary

Logic

UART

TXD0 O

UART0 data output pin. Allocated to the secondary function of the P43 pin

and the fourthly function of the P53 pin.

Secondary

Fourthly

Positive

RXD0 I

UART0 data input pin. Allocated to the primary function of the P02 pin and

the secondary function of the P42 pin.

Secondary Positive

TXD1 O

UART1 data output pin. Allocated to the secondary function of the P53 pin

and the fourthly function of the P43 pin.

Secondary

Fourthly

Positive

RXD1 I

UART1 data input pin. Allocated to the primary function of the P03 pin and

the secondary function of the P52 pin.

Secondary Positive

C bus interface

SDA I/O

C data input/output pin. This pin is used as the secondary function of the

P40 pin. This pin has an NMOS open drain output. When using this pin as

a function of the I

C, externally connect a pull-up resistor.

Secondary Positive

SCL I/O

C clock output pin. This pin is used as the secondary function of the P41

pin. This pin has an NMOS open drain output. When using this pin as a

function of the I

C, externally connect a pull-up resistor.

Secondary Positive

Synchronous serial (SSIO)

SIN0 I

Synchronous serial data input pin. Allocated to the tertiary function of the

P40 pin and P44 pin.

Tertiary Positive

SCK0 I/O

Synchronous serial clock input/output pin. Allocated to the tertiary function

of the P41 pin and P45 pin.

Tertiary —

SOUT0 O

Synchronous serial data output pin. Allocated to the tertiary function of the

P42 pin and P46 pin.

Tertiary Positive

SIN1 I

Synchronous serial data input pin. Allocated to the tertiary function of the

P50 pin .

Tertiary Positive

SCK1 I/O

Synchronous serial clock input/output pin. Allocated to the tertiary function

of the P51 pin.

Tertiary —

SOUT1 O

Synchronous serial data output pin. Allocated to the tertiary function of the

P52 pin.

Tertiary Positive

PWM

PWM4 O

PWM4 output pin. Allocated to the tertiary function of the P34 and P43 pins.

Tertiary Positive

PWM5 O

PWM5 output pin. Allocated to the tertiary function of the P35and P47 pins.

Tertiary Positive

T0P4CK I

External clock input pin for timer 0 and PWM4. Allocated to the primary

function of the P44 pin.

Primary —

T1P5CK I

External clock input pin for timer 1 and PWM5. Allocated to the primary

function of the P45 pin.

Primary —

PW45EV0

PW45EV1

Control start /stop pin for PWM4 and PWM5. Allocated to the primary

function of the P00 pin and P30 pin.

Primary —

External interrupt

NMI I

External non-maskable interrupt input pin. The interrupt occurs on both the

rising and falling edges.

Primary

Positive/

Negative

EXI0–EXI3 I

External maskable interrupt input pins. It is possible, for each bit, to specify

whether the interrupt is enabled and select the interrupt edge by software.

Allocated to the primary function of the P00–P03 pins.

Primary

Positive/

Negative

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P28

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ML610Q178 REFERENCE BOARD

ML610Q178 REFERENCE BOARD

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