FEDL610Q178FULL-01
ML610Q178
4/28
BLOCK DIAGRAM
Figure 1-1 is a block diagram of the ML610Q178.
Symbols with an asterisk “*” indicate that each of them is the secondary or tertiary function of the corresponding port.
Program
Memory
Flash
128Kbyte
RAM
4096byte
Interrupt
Controller
CPU (nX-U8/100) Large Model
Timing
Controller
EA
SP
Instruction
Decoder
BUS
Controller
Instruction
Register
TBC
INT
4
INT
6
8bit Timer
×6
GPIO
NMI
P20 to P23
INT
5
P50 to P53
Data-bus
TEST0
RESET_N
OSC
POWER
V
DDL
RESET &
TEST
ALU
EPSW13
PSW
ELR13
LR
ECSR13
DSR/CSR
PC
GREG
015
V
PP
V
DD
V
SS
OUTCLK*
UART
RXD0*
1
,
RXD1*
1
TXD0*
1
, TXD1*
1
INT
2
LSCLK*
P40 to P43
On-Chip
ICE
P00 to P03
SSIO
SCK0*
1
,
SCK1*
1
SIN0*
1
,
SIN1*
1
SOUT0*
1
,
SOUT1*
1
INT
2
WDT
INT
10bit-ADC
AIN0 to AIN15
*3
V
REF
V
DD
V
SS
OSC0*
1
INT
I
2
C
INT
1
SDA*
1
SCL*
1
PWM
INT
2
PWM4*
1
PWM5*
1
LCD
Driver
COM0 to COM3
SEG0 to SEG7
LCD
Drive Voltage
V
L1
, V
L2
, V
L3
XT0
XT1
P60 to P67
3
P90 to P93
BLD
PW45EV0*
1
P30 to P33
*3
INT
1
P10 to P11
P34 to P36
OSC1*
TEST1_N
P44 to P47
*3
SEG8 to SEG39
*2
PW45EV1*
1
PC0 to PC7
2
PD0 to PD7
2
PE0 to PE7
2
PF0 to PF7
2
*
1
Secondary or tertiary function
*
2
Select I/O port or LCD driver
*
3
Select I/O port or A/D converter input
FEDL610Q178FULL-01
ML610Q178
5/28
PIN CONFIGURATION
ML610Q178 QFP package product
NC: No Connection
PE1/SEG25
NMI
P03/INT3
P02/INT2
P01/INT1
P00/INT0
RESET
_
N
TEST0
PE7/SEG31
PE6/SEG30
PE5/SEG29
PE4/SEG28
PE3/SEG27
PE2/SEG26
PE0
/
SEG24
PD7/SEG23
PD6/SEG22
PD5/SEG21
PD4/SEG20
PF7/SEG39
PF6/SEG38
PF5/SEG37
PC5/SEG13
PC4/SEG12
PC3/SEG11
PC2/SEG10
PC1/SEG9
PC0/SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
P90/LED4
P91/LED5
P92/LED6
P
93/
LED7
P67/AIN15
P66/AIN14
P65/AIN13
P64/AIN12
V
SS
P33/AIN3
P32/AIN2
P31/AIN1
P30/AIN0
V
REF
P10/OSC0
P50/SIN1
P51/SCK1
P52/SOUT1
P53/TXD1
P34/PWM4
P35/PWM5
P36/LSCLK
P40/SDA
P41/SCL
P42/RXD0
P43/TXD0
V
DD
VPP
TEST1_N
V
DDL
XT1
XT0
VL1
VL2
VL3
P23/LED3
P22/LED2
P21/LED1
P20/LED0
P63/AIN11
P62/AIN10
P61/AIN9
P60/AIN8
P47/AIN7
P46/AIN6
P45/AIN5
PF4/SEG36
P44/AIN4
V
SS
PC7/SEG15
PC6/SEG14
1pin
100pin
30pin
31pin
50pin
51pin
81pin
80pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
61
60
59
58
57
55
54
53
52
51
71
70
69
68
67
66
65
64
63
62
80
79
78
77
76
75
74
73
72
56
90
89
88
87
86
85
84
83
82
81
100
99
98
97
96
95
94
93
92
91
COM3
COM2
COM1
COM0
PD2/SEG18
PD1/SEG17
PD0/SEG16
PD3/SEG19
PF3/SEG35
PF2/SEG34
PF1/SEG33
PF0/SEG32
P11/OSC1
FEDL610Q178FULL-01
ML610Q178
6/28
LIST OF PINS
Primary function Secondary function Tertiary function
Pin
No.
Pin
name
I/O Description
Pin
name
I/O Description
Pin
name
I/O Description
18,85 Vss
Negative power supply pin
19 V
DD
Positive power supply pin
20 V
DDL
Power supply for internal logic
(internally generated)
23 V
PP
Power supply pin for Flash ROM
24 V
L1
Power supply pin for LCD bias
25 V
L2
Power supply pin for LCD bias
26 V
L3
Power supply pin for LCD bias
14 TEST0 I/O
Input/output pin for testing
15 TEST1_N I/O
Input/output pin for testing
71 RESET_N I
Reset input pin
21
XT0 I
Low-speed clock oscillation pin
22
XT1 O
Low-speed clock oscillation pin
6
V
REF
I
Reference power supply pin of
Successive-approximation type
ADC
80 NMI I
Input port,
non-maskable interrupt
76
P00/EXI0/
PW45EV0
I
Input port /
External interrupt /
PW45EV0 input
77 P01/EXI1 I
Input port /
External interrupt
78
P02/EXI2/
RXD0
I
Input port /
External interrupt
UART0 data input
79
P03/EXI3/
RXD1
I
Input port /
External interrupt /
UART1 data input
16
P10 I Input port
OSC0 I
High-speed clock
oscillation pin
17
P11 I Input port
OSC1 O
High-speed clock
oscillation pin
81
P20/
LED0
O Output port / LED drive LSCLK O
Low-speed clock
output
82
P21/
LED1
O Output port / LED drive OUTCLK O
Low-speed clock
output
83
P22/
LED2
O Output port / LED drive
TM9OUT O Timer9 output
84
P23/
LED3
O Output port / LED drive
TMBOUT O TimerB output

ML610Q178 REFERENCE BOARD

Mfr. #:
Manufacturer:
Description:
ML610Q178 EVAL BRD
Lifecycle:
New from this manufacturer.
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