TDA9885HN/V5,118 Datasheet TDA9885TS/V3,112, TDA9885TS/V3,118, TDA9885HN/V3,118 | P10-P12

Product data sheet Rev. 03 — 16 December 2008 10 of 56

NXP Semiconductors

TDA9885; TDA9886

C-bus controlled multistandard alignment-free IF-PLL demodulators

8.6 AFC and digital acquisition help

Each relaxation oscillator of the VIF-PLL and FM-PLL demodulator has a wide frequency

range. To prevent false locking of the PLLs and with respect to the catching range, the

digital acquisition help provides an individual control, until the frequency of the VCO is

within the preselected standard dependent lock-in window of the PLL.

The in-window and out-window control at the FM PLL is additionally used to mute the

audio stage (if auto mute is selected via the I

C-bus).

The working principle of the digital acquisition help is as follows. The PLL VCO output is

connected to a down counter which has a predeﬁned start value (standard dependent).

The VCO frequency clocks the down counter for a ﬁxed gate time. Thereafter, the down

counter stop value is analyzed. In case the stop value is higher (lower) than the expected

value range, the VCO frequency is lower (higher) than the wanted lock-in window

frequency range. A positive (negative) control current is injected into the PLL loop ﬁlter

and consequently the VCO frequency is increased (decreased) and a new counting cycle

starts.

The gate time as well as the control logic of the acquisition help circuit is dependent on the

precision of the reference signal at pin REF. Operation as a crystal oscillator is possible as

well as connecting this input via a serial capacitor to an external reference frequency, e.g.

the tuning system oscillator.

The AFC signal is derived from the corresponding down counter stop value after a

counting cycle. The last four bits are latched and can be read out via the I

C-bus

(see Table 8). Also the digital-to-analog converted value is given as current at pin AFC.

8.7 Video demodulator and ampliﬁer

The video demodulator is realized by a multiplier which is designed for low distortion and

large bandwidth. The VIF signal is multiplied with the ‘in phase’ signal of the VIF-PLL

VCO.

The demodulator output signal is fed into the video preampliﬁer via a level shift stage with

integrated low-pass ﬁlter to achieve carrier harmonics attenuation.

The output signal of the preampliﬁer is fed to the VIF-AGC detector (see Section 8.3) and

in the sound trap mode also fed internally to the integrated sound carrier trap

(see Section 8.8). The differential trap output signal is converted to a single-ended signal

and ampliﬁed by the following post-ampliﬁer. The video output level at pin CVBS is

2 V (p-p).

In the trap bypass mode the output signal of the preampliﬁer is fed directly through the

post-ampliﬁer to pin CVBS. The output video level is 1.1 V (p-p) for using an external

sound trap with 10 % overall loss.

Noise clipping is provided in both cases.

Product data sheet Rev. 03 — 16 December 2008 11 of 56

NXP Semiconductors

TDA9885; TDA9886

C-bus controlled multistandard alignment-free IF-PLL demodulators

8.8 Sound carrier trap

The sound trap is constructed of three separate traps to realize sufﬁcient suppression of

the ﬁrst and second sound carriers.

For frequency control of the sound trap additionally a reference low-pass ﬁlter and a

phase detector are built in.

A sound carrier reference signal is fed into the reference low-pass ﬁlter and is shifted by

nominal 90 degrees. The phase detector compares the original reference signal with the

signal shifted by the reference ﬁlter and produces a DC voltage by charging or discharging

an integrated capacitor with a current proportional to the phase difference between both

signals, respectively to the frequency error of the integrated ﬁlters. The DC voltage

controls the frequency position of the reference ﬁlter and the sound trap. So the accurate

frequency position for the different standards is set by the sound carrier reference signal.

8.9 SIF ampliﬁer

The SIF ampliﬁer consists of three AC-coupled differential stages. Gain control is

performed by emitter degeneration and collector resistor variation. The total gain control

range is typically 66 dB. The differential input impedance is typically 2 kΩ in parallel with

3pF.

8.10 SIF-AGC detector

SIF gain control is performed by detection and controlling to a reference value of the

DC component of the AM demodulator output signal. This DC signal corresponds directly

to the SIF voltage at the output of the SIF ampliﬁer so that a constant SIF signal is

supplied to the AM demodulator and to the single reference QSS mixer.

By switching the gain of the input ampliﬁer of the SIF-AGC detector via the I

C-bus, the

internal SIF level for FM sound is 5.5 dB lower than for AM sound. This is to adapt the

SIF-AGC characteristic to the VIF-AGC characteristic. The adaption is ideal for a

picture-to-sound FM carrier ratio of 13 dB.

Via a comparator, the integrated AGC capacitor is charged or discharged for providing the

required SIF gain. Due to AM sound, the AGC reaction time is slow (f

< 20 Hz for the

closed AGC loop). For reducing this AM sound time constant in the event of a decreasing

IF amplitude step, the charge/discharge current of the AGC capacitor is increased (fast

mode) when the VIF-AGC detector (at positive modulation mode) operates in the fast

mode too. An additional circuit (threshold approximately 7 dB) ensures a very fast gain

reduction for a large increasing IF amplitude step.

8.11 Single reference QSS mixer

With the present system a high performance Hi-Fi stereo sound processing can be

achieved. For a simpliﬁed application without a SIF SAW ﬁlter, the single reference QSS

mixer can be switched to the intercarrier mode via the I

C-bus.

The single reference QSS mixer generates the 2nd FM TV sound intercarrier signal. It is

realized by a linear multiplier which multiplies the SIF ampliﬁer output signal and the

VIF-PLL VCO signal (90 degrees output) which is locked to the picture carrier. In this way

the QSS mixer operates as a quadrature mixer in the intercarrier mode and provides

suppression of the low frequency video signals.

Product data sheet Rev. 03 — 16 December 2008 12 of 56

NXP Semiconductors

TDA9885; TDA9886

C-bus controlled multistandard alignment-free IF-PLL demodulators

The QSS mixer output signal is fed internally via a high-pass and low-pass combination to

the FM demodulator as well as via an operational ampliﬁer to the intercarrier output

pin SIOMAD.

8.12 AM demodulator

The amplitude modulated SIF ampliﬁer output signal is fed both to a two-stage limiting

ampliﬁer that removes the AM and to a linear multiplier. The result of the multiplication of

the SIF signal with the limiter output signal is AM demodulation (passive synchronous

demodulator). The demodulator output signal is fed via a low-pass ﬁlter that attenuates

the carrier harmonics and through the input ampliﬁer of the SIF-AGC detector to the audio

ampliﬁer.

8.13 FM demodulator and acquisition help

The narrowband FM-PLL detector consists of:

• Gain controlled FM ampliﬁer and AGC detector

• Narrowband PLL

The 2nd SIF signal from the intercarrier mixer is fed to the input of an AC-coupled gain

controlled ampliﬁer with two stages. The gain controlled output signal is fed to the phase

detector of the narrowband FM PLL (FM demodulator). For good selectivity and

robustness against disturbance caused by the video signal, a high linearity of the gain

controlled FM ampliﬁer and of the phase detector as well as a constant signal level are

required. The gain control is done by means of an ‘in phase’ demodulator for the 2nd SIF

signal (from the output of the FM ampliﬁer). The demodulation output is fed into a

comparator for charging or discharging the integrated AGC capacitor. This leads to a

mean value AGC loop to control the gain of the FM ampliﬁer.

The FM demodulator is realized as a narrowband PLL with an external loop ﬁlter, which

provides the necessary selectivity (bandwidth approximately 100 kHz). To achieve good

selectivity, a linear phase detector and a constant input level are required. The gain

controlled intercarrier signal from the FM ampliﬁer is fed to the phase detector. The phase

detector controls via the loop ﬁlter the integrated low radiation relaxation oscillator. The

designed frequency range is from 4 MHz to 7 MHz.

The VCO within the FM PLL is phase-locked to the incoming 2nd SIF signal, which is

frequency modulated. As well as this, the VCO control voltage is superimposed by the

AF voltage. Therefore, the VCO tracks with the FM of the 2nd SIF signal. So, the

AF voltage is present at the loop ﬁlter and is typically 5 mV (RMS) for 27 kHz

FM deviation. This AF signal is fed via a buffer to the audio ampliﬁer.

The correct locking of the PLL is supported by the digital acquisition help circuit

(see Section 8.6).

8.14 Audio ampliﬁer and mute time constant

The audio ampliﬁer consists of two parts:

• AF preampliﬁer

• AF output ampliﬁer

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TDA9885HN/V5,118

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NXP Semiconductors

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IC IF-PLL DEMOD I2C-BUS 32-HVQFN

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