TDA9885_TDA9886_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 16 December 2008 19 of 56
NXP Semiconductors
TDA9885; TDA9886
I
2
C-bus controlled multistandard alignment-free IF-PLL demodulators
[1] For 0 dB refer to Section 12 symbol QV
TOP
.
9.2.4 Data byte for data mode (E data)
[1] For positive modulation choose 6.5 MHz.
[1] The corresponding port function has to be disabled (set to ‘high-impedance’); see Table 10 and Table
note 12 of Table 20.
00101−11
00100−12
00011−13
00010−14
00001−15
00000−16
Table 12. Tuner takeover point adjustment bits
…continued
Bit TOP adjustment (dB)
C4 C3 C2 C1 C0
Table 13. Bit description of SAD register for data mode (SAD = 10)
Bit Symbol Description
7 E7 VIF AGC and port features; dependent on bit E5; see
Table 14
6 E6 L standard PLL gating
1 = gating in case of 36 % positive modulation
0 = gating in case of 0 % positive modulation
5 E5 VIF, SIF and tuner minimum gain; dependent on bit E7; see
Table 14
4 to 2 E[4:2] vision intermediate frequency selection; see
Table 15
1 and 0 E[1:0] sound intercarrier frequency selection (sound 2nd IF)
00=f
FM
= 4.5 MHz
01=f
FM
= 5.5 MHz
10=f
FM
= 6.0 MHz
11=f
FM
= 6.5 MHz
[1]
Table 14. Options in extended TV mode; bit B3 = 0 of SAD 00 register
Function Bit E7 = 0 Bit E7 = 1
Bit E5 = 0 Bit E5 = 1 Bit E5 = 0 Bit E5 = 1
Pin OP1 port function port function port function VIF-AGC external input
[1]
Pin OP2 port function port function VIF-AGC output
[1]
port function
Gain normal gain minimum gain normal gain external gain
