LTC4259A-1
13
4259a1fa
involves reading the register to determine its status, set-
ting the appropriate bit in software and writing back the
entire register, a pushbutton register allows a single bit to
be written without knowing or affecting the status of the
other bits in the register. Pushbutton registers are write-
only and will return 00h if read.
Det/Class Restart PB (Address 18h): Detection/Classifi-
cation Restart Pushbutton Register, Write Only. Writing a
1 to any bit in this register will start or restart a single
detection or classification cycle at the corresponding port
in Manual mode. It can also be used to set the correspond-
ing bits in the Detect/Class Enable register (address 14h)
for ports in auto or semiauto mode. The lower 4 bits affect
detection on each port while the upper 4 bits affect
classification.
Power Enable PB (Address 19h): Power Enable Pushbutton
Register, Write Only. The lower four bits of this register set
the Power Enable bit in the corresponding Port Status reg-
ister; the upper four bits clear the corresponding Power
Enable bit. Setting or clearing the Power Enable bits via this
register will turn on or off the power in any mode except
shutdown, regardless of the state of detection or classifi-
cation. Note that t
ICUT
, t
START
and disconnect events (if
enabled) will still turn off power if they occur.
The Power Enable bit cannot be set if the port has turned
off due to a t
ICUT
or t
START
fault and the t
ICUT
timer has not
yet counted back to zero. See Applications Information for
more information on t
ICUT
timing.
Clearing the Power Enable bits with this register also
clears the detect and fault event bits, the Port Status
register, and the Detection and Classification Enable bits
for the affected port(s).
Reset PB (Address 1Ah): Reset Pushbutton, Write Only.
Bits 0-3 reset the corresponding port by clearing the power
enable bit, the detect and fault event bits, the status regis-
ter and the detection and classification enable bits for that
port. Bit 4 returns the entire LTC4259A-1 to the power-on
reset state; all ports are turned off, the AUTO pin is reread
and all registers are returned to their power-on defaults,
except V
DD
UVLO, which remains cleared. Bit 5 is reserved;
setting it has no effect. Setting bit 6 releases the Interrupt
pin if it is asserted without affecting the Event registers or
the Interrupt register. When the INT pin is released in this
Detect/Class Enable (Address 14h): Detection and Clas-
sification Enable, Read/Write. The lower four bits of this reg-
ister enable the detection circuitry at the corresponding port
if that port is in Auto or Semiauto mode. The upper four bits
enable the classification circuitry at the corresponding port
if that port is in Auto or Semiauto mode. In manual mode,
setting a bit in this register will cause the LTC4259A-1 to
perform one classification or detection cycle on the corre-
sponding port. Writing to the Detect/Class Restart PB (18h)
has the same effect without disturbing the Detect/Class
Enable bits for other ports.
Timing Config (Address 16h): Global Timing Configuration,
Read/Write. Bits 0-1 program t
DIS
, the time duration before
a port is automatically tuned off after the PD is removed.
The LTC4259A-1 can be programmed to monitor whether
port current is below I
MIN
(DC connect) or port impedance
is high (AC disconnect). Bits 2-3 program t
ICUT
, the time
during which a port’s current can exceed I
CUT
without it
being turned off. If the current is still above I
CUT
after t
ICUT
,
the LTC4259A-1 will indicate a t
ICUT
fault and turn the port
off. Bits 4-5 program t
START
, the time duration before an
overcurrent condition during port power-on is considered
a t
START
fault and the port is turned off. Note that using the
t
ICUT
and t
START
times other than the default is not compli-
ant with IEEE 802.3af and may double or quadruple the
energy dissipated by the external MOSFETs during fault con-
ditions. Bits 6-7 are reserved and should be read/written
as 0. See Electrical Characteristics for timer bit encoding.
Also see the Applications Information for descriptions of
t
START
, t
ICUT
, DC and AC disconnect timing.
Misc Config (Address 17h): Miscellaneous Configuration,
Read/Write. Bit 5 is the Osc Fail Mask; it is set by default.
When the Osc Fail Mask bit is clear, it prevents a failure on
the OSCIN pin from setting the Osc Fail bit and causing a
Supply Event Interrupt. Setting bit 7 enables the INT pin.
If this bit is reset, the LTC4259A-1 will not pull down the
INT pin in any condition nor will it respond to the Alert Re-
sponse Address. This bit is set by default.
Pushbutton Registers
Note Regarding Pushbutton Registers: “Pushbutton” reg-
isters are specialized registers that trigger an event when
a 1 is written to a bit; writing a 0 to a bit will do nothing. Unlike
a standard read/write register, where setting a single bit
REGISTER FU CTIO S
UU
