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NB3F8L3010CMNR4G

P1-P3P4-P6P7-P9P10-P12P13-P13
NB3F8L3010C
www.onsemi.com
10
Figure 7. General Diagram for LVCMOS Driver to XTAL Input Interface Use Rs or R1 / R2
Figure 8. General Diagram for LVPECL Driver to XTAL Input Interface
Z
o
= 50 W
LVMOS
C1
0.1 mF
R2
100 W
Z
0
= R
O
+ R
s
GND = 0.0 V
V
DD
R1
100 W
R
s
R
O
GND = 0.0 V
XTAL_IN
V
DD
XTAL_OUT
Z
o
= 50 W
LVPECL
C1
0.1 mF
V
TT
= V
DD
− 2.0 V
V
DD
GND = 0.0 V
XTAL_IN
XTAL_OUT
Z
o
= 50 W
50 W 50 W
NB3F8L3010C
www.onsemi.com
11
Differential Clock Input Interface
The CLK / CLK accept LVDS, LVPECL, SSTL, HCSL
differential signals. Signals must meet the V
PP
and VCMR
input requirements. Figures 9 to 13 show interface
examples for the CLK / CLK
input with built−in 50 W
terminations driven by the most common driver types. The
input interfaces suggested here are examples only. If the
driver is from another vendor, use their termination
recommendation. Please consult with the vendor of the
driver component to confirm the driver termination
requirements.
Figure 9. CLK / CLK Input Driven by 3.3 V LVPECL
Driver (Thevenin Parallel Termination)
Figure 10. CLK / CLK Input Driven by 3.3 V
LVPECL Driver (“Y” Parallel Termination)
Figure 11. CLK / CLK
Input Driven by a 3.3 V
HCSL Driver
Figure 12. CLK / CLK Input Driven by 3.3 V
LVDS Driver
Figure 13. CLK / CLK
Input Driven by 2.5 V SSTL Driver
Z
o
= 50 W
LVPECL
84 W
GND = 0.0 V
84 W
Z
o
= 50 W
Differential
In
Q
x
Q
x
CLKx
CLKx
Z
o
= 50 W
LVPECL
50 W
GND = 0.0 V
50 W
Z
o
= 50 W
Differential
In
Q
x
Q
x
CLKx
CLKx
V
DD
= +3.3 V
125 W125 W
GND = 0.0 V
V
DD
= +3.3 V
GND = 0.0 V
V
DD
= +3.3 V
50 W
GND = 0.0 V
V
DD
= +3.3 V
GND = 0.0 V
V
DD
= +3.3 V
Z
o
= 50 W
HCSL
50 W
GND = 0.0 V
50 W
Z
o
= 50 W
Differential
In
Q
x
Q
x
CLKx
CLKx
GND = 0.0 V
V
DD
= +3.3 V
GND = 0.0 V
V
DD
= +3.3 V
33 W (Opt)
33 W (Opt)
Z
o
= 50 W
SSTL
120 W
GND = 0.0 V
120 W
Z
o
= 50 W
Differential
In
Q
x
Q
x
CLKx
CLKx
V
DD
= +2.5 V
120 W
120 W
GND = 0.0 V
V
DD
= +3.3 V
GND = 0.0 V
V
DD
= +2.5 V
Z
o
= 50 W
LVDS
100 W
Z
o
= 50 W
Differential
In
Q
x
Q
x
CLKx
CLKx
GND = 0.0 V
V
DD
= +3.3 V
GND = 0.0 V
V
DD
= +3.3 V
NB3F8L3010C
www.onsemi.com
12
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the
package and the electrical performance, a land pattern must
be incorporated on the Printed Circuit Board (PCB) within
the footprint of the package corresponding to the exposed
metal pad or exposed heat slug on the package, as shown in
Figure 14. The solderable area on the PCB, as defined by the
solder mask, should be at least the same size/shape as the
exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should
be designed on the PCB between the outer edges of the land
pattern and the inner edges of pad pattern for the leads to
avoid any shorts. While the land pattern on the PCB provides
a means of heat transfer and electrical grounding from the
package to the board through a solder joint, thermal vias are
necessary to effectively conduct from the surface of the PCB
to the ground plane(s). The land pattern must be connected
to ground through these vias. The vias act as “heat pipes”.
The number of vias (i.e. “heat pipes”) is application specific
and dependent upon the package power dissipation as well
as electrical conductivity requirements. Thus, thermal and
electrical analysis and/or testing are recommended to
determine the minimum number needed. Maximum thermal
and electrical performance is achieved when an array of vias
is incorporated in the land pattern. It is recommended to use
as many vias connected to ground as possible. It is also
recommended that the via diameter should be 12 to 13 mils
(0.30 to 0.33 mm) with 1 oz copper via barrel plating. This
is desirable to avoid any solder wicking inside the via during
the soldering process which may result in voids in solder
between the exposed pad/slug and the thermal land.
Precautions should be taken to eliminate any solder voids
between the exposed heat slug and the land pattern. Note:
These recommendations are to be used as a guideline only.
Figure 14. Suggested Assembly for Exposed Pad Thermal Release Path – Cut−away View (not to scale)
ORDERING INFORMATION
Device Package Shipping
†
NB3F8L3010CMNG QFN32
(Pb−Free)
74 Units / Rail
NB3F8L3010CMNR4G QFN32
(Pb−Free)
1000 / Tape & Reel
NB3F8L3010CMNTWG QFN32
(Pb−Free)
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
P1-P3P4-P6P7-P9P10-P12P13-P13

NB3F8L3010CMNR4G

Mfr. #:
Buy NB3F8L3010CMNR4G
Manufacturer:
ON Semiconductor
Description:
Clock Buffer 1:10 LVCMOS FANOUT BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
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