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NB3F8L3010CMNR4G

P1-P3P4-P6P7-P9P10-P12P13-P13
NB3F8L3010C
www.onsemi.com
4
FUNCTION TABLES
Table 3. CLOCK ENABLE (SELx) FUNCTION TABLE
SEL[1:0] Input Selected Input Clock
00 CLK0/CLK0
01 CLK1/CLK1
10 Crystal Osc Input
11 Crystal Osc Input
Table 4. CLOCK OUTPUT ENABLE (OE) FUNCTION
TABLE
OE Input Q[9:0] Output
0 High Impedance
1 Outputs Enabled
Table 5. DIFF IN/OUT TABLE (Diff or S.E.)
Input Condition Output
CLK0/1; CLK0/1 = OPEN Logic LOW
CLK0/1; CLK0/1 = GND Undefined
CLK0/1 = HIGH; CLK0/1 = LOW Logic HIGH
CLK0/1 = LOW; CLK0/1 = HIGH Logic LOW
Table 6. CRYSTAL CHARACTERISTICS
Parameter Min Typ Max Unit
Mode of Oscillation Fundamental
Frequency 10 50 MHz
Equivalent Series Resistance (ESR) 50
W
Shunt Capacitance 7 pF
Drive Power 100
mW
Table 7. ATTRIBUTES
Characteristic Value
ESD Protection Human Body Model
Machine Model
>2 kV
200 V
Moisture Sensitivity (Note 2) QFN32 Level 3
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
Transistor Count 474 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Table 8. MAXIMUM RATINGS (Note 3)
Symbol
Parameter Condition Rating Unit
V
DD
,
VDDO
n
Positive Power Supply GND = 0 V 4.6 V
V
I
Input Voltage
XTAL_IN
Diff, SELx, OE Inputs
0 v V
I
v V
DD
–0.5 v V
I
v V
DD
+ 0.5
V
V
O
Output Voltage – 0.5 v V
O
v VDDO
n
+ 0.5 V
T
A
Operating Temperature Range, Industrial −40 to +85
_C
T
stg
Storage Temperature Range −65 to +150
_C
θ
JA
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
31
27
_C/W
θ
JC
Thermal Resistance (Junction−to−Case) (Note 3) 12
_C/W
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
NB3F8L3010C
www.onsemi.com
5
Table 9. POWER SUPPLY DC CHARACTERISTICS V
DD
= 3.3 V ± 5% (3.135 V to 3.465 V) or V
DD
= 2.5 V ±5% (2.375 V to
2.625 V) and VDDO
n
= 3.3 V ± 5% (3.135 V to 3.465 V) or 2.5 V ± 5% (2.375 V to 2.625 V) or 1.8 V ± 0.2 V (1.6 V to 2.0 V) or 1.5 V ±
0.15 V (1.35 V to 1.65 V); T
A
= −40°C to 85°C
Symbol
Parameter Test Conditions Min Typ Max Unit
IDD VDD Power Supply
Current
OE = 0, no load
3.3 V ± 5%; VDDO
n
= 3.3 V ± 5% or 2.5 V ± 5% or
1.8 V ± 0.2 V or 1.5 V ± 0.15 V
2.5 V ± 5%; VDDO
n
= 2.5 V ± 5% or 1.8 V ± 0.2 V
or 1.5 V ± 0.15 V
30 50 mA
IDDO VDDO Power Supply
Current
OE = 0, no load
3.3 V ± 5%; VDDO
n
= 3.3 V ± 5% or 2.5 V ± 5% or
1.8 V ± 0.2 V or 1.5 V ± 0.15 V
2.5 V ± 5%; VDDO
n
= 2.5 V ± 5% or 1.8 V ± 0.2 V
or 1.5 V ± 0.15 V
5 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
Table 10. DC CHARACTERISTICS T
A
= −40°C to 85°C
Symbol
Parameter Test Conditions Min Typ Max Unit
V
IH
LVCMOS / LVTTL Input High Voltage
(OE, SELx)
V
DD
= 3.3 V ±5%
V
DD
= 2.5 V ± 5%
2
1.7
V
DD
+ 0.3
V
DD
+ 0.3
V
V
IL
LVCMOS / LVTTL Input Low Voltage
(OE, SELx)
V
DD
= 3.3 V ±5%
V
DD
= 2.5 V ± 5%
−0.3
−0.3
0.8
0.7
V
I
IH
Input High Current
OE, SELx,
CLKx/CLKx
V
DD
= V
IN
= 3.465 V
V
DD
= V
IN
= 3.465 V or 2.625 V
150
150
mA
I
IL
Input Low Current
OE, SELx
CLKx
CLKx
V
DD
= 3.465 V; V
IN
= 0.0 V
V
DD
= 3.465 V or 2.625 V V
IN
= 0.0 V
V
DD
= 3.465 V or 2.625 V V
IN
= 0.0 V
−5
−5
−150
mA
V
OH
Output High Voltage (Note 4)
VDDO
n
= 3.3 V ± 5% 2.6
V
VDDO
n
= 2.5 V ± 5% 1.8
VDDO
n
= 1.8 V ± 0.2 V 1.2
VDDO
n
= 1.5 V ± 0.15 V 0.9
V
OL
Output Low Voltage (Note 4)
VDDO
n
= 3.3 V ± 5% or 2.5 V ± 5% 0.5
V
VDDO
n
= 1.8 V ± 0.2 V 0.4
VDDO
n
= 1.5 V ± 0.15 V 0.37
V
PP
Peak−to−Peak Input Voltage
V
IL
> −0.3 V CLKx/CLKx
V
DD
= 3.3 V ±5% or V
DD
= 2.5 V ± 5% 0.15 1.3 V
V
IHCMR
Input High Level Common Mode
Range
V
CM
= V
IH
; V
IL
> −0.3 V CLKx/CLKx
V
DD
= 3.3 V ±5% or V
DD
= 2.5 V ± 5% 0.5 V
DD
− 0.85 V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
4. Outputs terminated with 50 W to VDDO
n
/2. See Parameter Measurement Information..
Table 11. AC CHARACTERISTICS V
DD
= 3.3 V ± 5% (3.135 V to 3.465 V) or V
DD
= 2.5 V ±5% (2.375 V to 2.625 V) and
VDDO
n
= 3.3 V ± 5% (3.135 V to 3.465 V) or 2.5 V ± 5% (2.375 V to 2.625 V) or 1.8 V ± 0.2 V (1.6 V to 2.0 V) or 1.5 V ± 0.15 V (1.35 V
to 1.65 V); T
A
= −40°C to 85°C
Symbol
Parameter Test Conditions Min Typ Max Unit
f
MAX
Output Frequency
Using External
Crystal
10 50 MHz
Using External
Clock Source
(Note 5)
DC 200 MHz
NB3F8L3010C
www.onsemi.com
6
Table 11. AC CHARACTERISTICS V
DD
= 3.3 V ± 5% (3.135 V to 3.465 V) or V
DD
= 2.5 V ±5% (2.375 V to 2.625 V) and
VDDO
n
= 3.3 V ± 5% (3.135 V to 3.465 V) or 2.5 V ± 5% (2.375 V to 2.625 V) or 1.8 V ± 0.2 V (1.6 V to 2.0 V) or 1.5 V ± 0.15 V (1.35 V
to 1.65 V); T
A
= −40°C to 85°C
Symbol UnitMaxTypMinTest ConditionsParameter
t
sk(o)
Output Skew (Notes 6 and 7) 10 55 ps
t
JITTER
F
Additive RMS
Phase Jitter
(Integrated
12 kHz *
20 MHz)
(Note 8)
Input clock from
CLK0/CLK0 or
CLK1/CLK1
VDDO
n
= 3.3 V ± 5% 0.03
ps
VDDO
n
= 2.5 V ± 5% 0.03
VDDO
n
= 1.8 V ± 0.2 V 0.03
VDDO
n
= 1.5 V ± 0.15 V 0.03
External clock
over drives
crystal interface
VDDO
n
= 3.3 V ± 5% 0.03
VDDO
n
= 2.5 V ± 5% 0.03
VDDO
n
= 1.8 V ± 0.2 V 0.03
VDDO
n
= 1.5 V ± 0.15 V 0.03
Input clock from
crystal
VDDO
n
= 3.3 V ± 5% 0.03
VDDO
n
= 2.5 V ± 5% 0.03
VDDO
n
= 1.8 V ± 0.2 V 0.03
VDDO
n
= 1.5 V ± 0.15 V 0.03
t
R
/ t
F
Output Rise/Fall Time (20% and 80%)
VDDO
n
= 3.3 V ± 5% 150 350 500
ps
VDDO
n
= 2.5 V ± 5% 150 350 500
VDDO
n
= 1.8 V ± 0.2 V 150 350 600
VDDO
n
= 1.5 V ± 0.15 V 150 350 600
odc Output Duty Cycle
VDDO
n
= 3.3 V ± 5% 45 55
%
VDDO
n
= 2.5 V ± 5% 40 60
VDDO
n
= 1.8 V ± 0.2 V 40 60
VDDO
n
= 1.5 V ± 0.15 V 40 60
t
EN
Output Enable
Time (Note 9)
OE 4 cycles
t
DIS
Output Disable
Time (Note 9)
OE 4 cycles
MUX_
ISOLATION
MUX_
ISOLATION
155.52 MHz 55 dB
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
5. XTAL_IN can be overdriven relative to a signal a crystal would provide.
6. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO
n
/2.
7. This parameter is defined in accordance with JEDEC Standard 65.
8. See phase noise plot.
9. These parameters are guaranteed by characterization. Not tested in production. See Parameter Measurement Information
P1-P3P4-P6P7-P9P10-P12P13-P13

NB3F8L3010CMNR4G

Mfr. #:
Buy NB3F8L3010CMNR4G
Manufacturer:
ON Semiconductor
Description:
Clock Buffer 1:10 LVCMOS FANOUT BUFFER
Lifecycle:
New from this manufacturer.
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