85222AMI-02LF

ICS85222I-02 Data Sheet 1-TO-2, LVCMOS/LVTTL -TO- DIFFERENTIAL HSTL TRANSLATOR
ICS85222AMI-02 APRIL 25, 2014 4 ©2014 Integrated Device Technology, Inc.
AC Electrical Characteristics
Table 4. AC Characteristics, V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All outputs must be terminated with 50 to ground.
NOTE 1: Measured from V
DD
/2 of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using
the same type of inputs on each device, the outputs are measured at the differential crosspoints.
Parameter Symbol Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 350 MHz
t
PD
Propagation Delay; NOTE 1 ƒ 350MHz 1.0 1.55 ns
tsk(o) Output Skew; NOTE 2, 3 35 ps
tsk(pp) Part-to-Part Skew; NOTE 4 500 ps
t
R
/t
F
Output Rise/Fall Time 20% to 80% 225 700 ps
odc Output Duty Cycle
ƒ 250MHz 40 60 %
ƒ 250MHz 35 65 %
ICS85222I-02 Data Sheet 1-TO-2, LVCMOS/LVTTL -TO- DIFFERENTIAL HSTL TRANSLATOR
ICS85222AMI-02 APRIL 25, 2014 5 ©2014 Integrated Device Technology, Inc.
Parameter Measurement Information
3.3V Core/3.3V Output Load AC Test Circuit
Output Skew
Output Duty Cycle/Pulse Width/Period
Part-to-Part Skew
Propagation Delay
Output Rise/Fall Time
SCOPE
Qx
nQx
HSTL
GND
3.3V±5%
0V
V
DD
nQx
Qx
nQy
Qy
nQ0,nQ1
Q0,Q1
tsk(pp)
Part 1
Part 2
nQx
Qx
nQy
Qy
t
PD
V
DD
2
CLK
Q0, Q1
nQ0, nQ1
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SWING
ICS85222I-02 Data Sheet 1-TO-2, LVCMOS/LVTTL -TO- DIFFERENTIAL HSTL TRANSLATOR
ICS85222AMI-02 APRIL 25, 2014 6 ©2014 Integrated Device Technology, Inc.
Application Information
Recommendations for Unused Input and Output Pins
Outputs:
HSTL Outputs
All outputs must be terminated with 50to ground.
Schematic Example
Figure 1 shows a schematic example of ICS85222I-02. In the
example, the input is driven by a 7 LVCMOS driver with a series
termination. The decoupling capacitor should be physically located
near the power pin. For ICS85222I-02, the unused output need to be
terminated.
Figure 1. ICS85222I-02 HSTL Buffer Schematic Example
Zo = 50 Ohm
R3
50
R4
50
R2
50
VDD=3.3V
C1
0.1u
Zo = 50 Ohm
R6 43
Zo = 50 Ohm
Zo = 50 Ohm
R1
50
HSTL Input
+
-
Ro ~ 7 Ohm
Q2
Driv er_LVCMOS
Zo = 50 Ohm
U1
ICS85222-02
1
2
3
4
8
7
6
5
Q0
nQ0
Q1
nQ1
VDD
CLK
nc
GND
HSTL Input
+
-
VDD=3.3V

85222AMI-02LF

Mfr. #:
Manufacturer:
IDT
Description:
Translation - Voltage Levels Dual LVCMOS Translator 2 Input
Lifecycle:
New from this manufacturer.
Delivery:
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