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NB3N1900KMNTWG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
NB3N1900K
www.onsemi.com
13
Rs
Rs
Rp Rp
10 inches
Differential Zo
2pF 2pF
HCSL Output
Buffer
Figure 3. NB3N1900K Differential Test Loads
Table 18. DIFFERENTIAL OUTPUT TERMINATION TABLE
DIF Zo (W) Iref (W) Rs (W) Rp (W)
100 475 33 50
85 412 27 42.2 or 43.2
PWRGD/PWRDN#
PWRGD/PWRDN# is a dual function pin. PWRGD is
asserted high and de−asserted low. De−assertion of PWRGD
(pulling the signal low) is equivalent to indicating a
powerdown condition. PWRGD (assertion) is used by the
NB3N1900K to sample initial configurations such as
frequency select condition and SA selections.
After PWRGD has been asserted high for the first time,
the pin becomes a PWRDN# (Power Down) pin that can be
used to shut off all clocks cleanly and instruct the device to
invoke power savings mode. PWRDN# is a completely
asynchronous active low input. When entering power
savings mode, PWRDN# should be asserted low prior to
shutting off the input clock or power to ensure all clocks
shut down in a glitch free manner. When PWRDN# is
asserted low by two consecutive rising edges of DIF#, all
differential outputs are held tri−stated on the next DIF# high
to low transition. The assertion and de-assertion of
PWRDN# is absolutely asynchronous.
WARNING: Disabling of the CLK_IN input clock prior
to assertion of PWRDN# is an undefined
mode and not recommended. Operation in
this mode may result in glitches, excessive
frequency shifting, etc.
Table 19. PWRGD/PWRDN# FUNCTIONALITY
PWRGD/PWRDN# DIF DIF#
0 Tri−state Tri−state
1 Running Running
NB3N1900K
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14
Buffer Power−Up State Machine
Table 20. BUFFER POWER−UP STATE MACHINE
State Description
0
3.3 V Buffer power off
1 After 3.3 V supply is detected to rise above 3.135 V, the buffer enters State 1 and initiates a 0.1 ms–0.3 ms delay.
2 Buffer waits for a valid clock on the CLK input and PWRDN# de−assertion (or PWRGD assertion low to high)
3 Once the PLL is locked to the CLK_IN input clock, the buffer enters state 3 and enables outputs for normal operation.
(Notes 46, 47)
46.The total power up latency from power on to all outputs active must be less than 1.8 ms (assuming a valid clock is present on CLK_IN input).
47.If power is valid and powerdown is de−asserted (PWRGD asserted) but no input clocks are present on the CLK_IN input, DIF clocks must
remain disabled. Only after valid input clocks are detected, valid power, PWRDN# de−asserted (PWRGD asserted) with the PLL
locked/stable and the DIF outputs enabled.
Figure 4. Buffer Power−Up State Diagram
State 0 State 3
Power Off
Normal
Operation
State 1
Delay
0.1 ms − 0.3 ms
State 2
Powerdown Asserted
Wait for input
clock and
powerdown
de−assertion
No input clock
Device Power−Up Sequence
Follow the power−up sequence below for proper device
functionality:
1. PWRGD/PWRDN# pin must be Low.
2. Assign remaining control pins to their required
state (100M_133M#, HBW_BYPASS_LBW#,
SDA, SCL)
3. Apply power to the device.
4. Once the VDD pin has reached a valid VDDmin
level (3.3V −5%), the PWRGD/PWRDN# pin
must be asserted High. See Figure 5.
Note: If no clock is present on the CLK_IN/CLK_IN#
pins when device is powered up, there will be no clock on
DIF/DIF# outputs.
Figure 5. PWRGD and VDD Relationship Diagram
NB3N1900K
www.onsemi.com
15
GENERAL SMBUS SERIAL INTERFACE INFORMATION FOR THE NB3N1900K
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address XX
(H)
• Clock(device) will acknowledge
• Controller (host) sends the beginning byte location = N
• Clock(device) will acknowledge
• Controller (host) sends the data byte count = X
• Clock(device) will acknowledge
• Controller (host) starts sending Byte N through Byte
N + X − 1
• Clock(device) will acknowledge each byte one at a
time
• Controller (host) sends a Stop bit
Table 21. INDEX BLOCK WRITE OPERATION
Controller (Host) Clock (Device)
T starT bit
Slave Address XX
(H)
WR WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
X Byte
ACK
O O
O O
O
Byte N + X - 1
ACK
P stoP bit
Note: XX
(H)
is defined by SMBus address select pins
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address XX
(H)
• Clock(device) will acknowledge
• Controller (host) sends the beginning byte location = N
• Clock(device) will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address YY
(H)
• Clock(device) will acknowledge
• vclock will send the data byte count = X
• Clock(device) sends Byte N + X −1
• Clock(device) sends Byte 0 through byte X (if X
(H)
was
written to byte 8).
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a not acknowledge bit
• Controller (host) sends a Stop bit
Table 22. INDEX BLOCK READ OPERATION
Controller (Host) Clock (Device)
T starT bit
Slave Address XX
(H)
WR WRite
ACK
Beginning Byte = N
ACK
RT Repeat starT
Slave Address YY
(H)
RD ReaD
ACK
Data Byte Count = X
ACK
X Byte
Beginning Byte N
ACK
O
O O
O O
O
Byte N + X - 1
N
Not
acknowledge
P stoP bit
Note: XX
(H)
is defined by SMBus address select pins
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

NB3N1900KMNTWG

Mfr. #:
Buy NB3N1900KMNTWG
Manufacturer:
ON Semiconductor
Description:
Clock Buffer 3.3V 1:19 HCSL FANOU
Lifecycle:
New from this manufacturer.
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