NB3N1900K
www.onsemi.com
7
Table 8. ABSOLUTE MAXIMUM RATINGS (Note 1)
Symbol
Parameter Conditions Min Typ Max Unit
V
DDA
3.3 V Core Supply Voltage (Note 2) 4.6 V
V
DD
3.3 V Logic Supply Voltage (Note 2) 4.6 V
V
IL
Input Low Voltage
GND −
0.5
V
V
IH
Input High Voltage Except for SMBus interface
V
DD
+
0.5
V
V
IHSMB
Input High Voltage SMBus clock and data pins 5.5 V
T
s
Storage Temperature −65 150 °C
T
J
Junction Temperature 125 °C
T
c
Case Temperature 130 °C
ESD ESD protection Human Body Model 2000 V
qJA
Thermal Resistance Junction−to−Ambient
Still air 18.1 °C/W
qJC
Thermal Resistance Junction−to−Case 5.0 °C/W
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Guaranteed by design and characterization, not tested in production.
2. Operation under these conditions is neither implied nor guaranteed.
NB3N1900K
www.onsemi.com
8
Table 9. ELECTRICAL CHARACTERISTICS − INPUT/SUPPLY/COMMON PARAMETERS
(V
DD
= V
DDA
= 3.3 V ±5%, T
A
= −10°C to +70°C), See Test Loads for Loading Conditions.
Symbol
Parameter Conditions Min Typ Max Unit
V
IH
Input High Voltage
Single−ended inputs, except SMBus, low
threshold and tri−level inputs (Note 3)
2
V
DD
+
0.3
V
V
IL
Input Low Voltage
Single−ended inputs, except SMBus, low
threshold and tri−level inputs (Note 3)
GND −
0.3
0.8 V
V
IH_FS
(Note 4)
Input High Voltage 0.7
V
DD
+
0.3
V
V
IL_FS
(Note 4)
Input Low Voltage
GND −
0.3
0.35 V
I
IN
Input Current
Single−ended inputs, V
IN
= GND, V
IN
= V
DD
(Note 3)
−5 5
mA
F
IBYP
Input Frequency
V
DD
= 3.3 V, Bypass mode (Notes 3, 5 and 6) 33 400 MHz
F
IPLL
V
DD
= 3.3 V, 100.00 MHz PLL mode (Note 5) 99 100.00 101 MHz
F
IPLL
V
DD
= 3.3 V, 133.33 MHz PLL mode (Notes 5) 132.33 133.33 134.33 MHz
L
PIN
Pin Inductance (Note 3) 7 nH
C
IN
Capacitance
Logic Inputs, except CLK_IN (Note 3) 1.5 5 pF
C
INDIF_IN
CLK_IN differential clock inputs
(Notes 3 and 7)
1.5 2.7 pF
C
OUT
Output pin capacitance (Note 3) 6 pF
T
STAB
Clk Stabilization
From V
DD
Power−Up and after input clock
stabilization or de−assertion of PD# to 1st
clock (Notes 3 and 5)
1.8 ms
f Input SS Modulation Frequency
Allowable Frequency (Triangular Modulation)
(Note 3)
30 33 kHz
t
LATOE#
OE# Latency
DIF start after OE# assertion DIF stop after
OE# de−assertion (Note 3)
4 12 cycles
t
DRVPD
Tdrive_PD#
DIF output enable after PD# de−assertion
(Note 3)
300
ms
t
F
Tfall Fall time of control inputs (Notes 3 and 5) 5 ns
t
R
Trise Rise time of control inputs (Notes 3 and 5) 5 ns
V
ILSMB
SMBus Input Low Voltage (Note 3) 0.8 V
V
IHSMB
SMBus Input High Voltage (Note 3) 2.1 V
DDSMB
V
V
OLSMB
SMBus Output Low Voltage @ I
PULLUP
(Note 3) 0.4 V
I
PULLUP
SMBus Sink Current @ V
OL
(Note 3) 4 mA
V
DDSMB
Nominal Bus Voltage 3 V to 5 V ±10% (Note 3) 2.7 5.5 V
t
RSMB
SCL/SDA Rise Time (Max V
IL
− 0.15) to (Min V
IH
+ 0.15) (Note 3) 1000 ns
t
FSMB
SCL/SDA Fall Time (Min VIH + 0.15) to (Max V
IL
− 0.15) (Note 3) 300 ns
f
MAXSMB
SMBus Operating Frequency
Maximum SMBus operating frequency
(Notes 3 and 8)
100 kHz
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Guaranteed by design and characterization, not tested in production.
4. 100M_133M# Frequency Select (FS).
5. Control input must be monotonic from 20% to 80% of input swing.
6. Fmax measured until output violates output duty cycle specifications and output V
High
, V
Low
specification.
7. CLK_IN input
8. The differential input clock must be running for the SMBus to be active.
NB3N1900K
www.onsemi.com
9
Table 10. ELECTRICAL CHARACTERISTICS − CLOCK INPUT PARAMETERS
(V
DD
= V
DDA
= 3.3 V ±5%, T
A
= −10°C to +70°C), See Test Loads for Loading Conditions.
Symbol
Parameter Conditions Min Typ Max Unit
V
IHDIF
Input High Voltage − CLK_IN
(Note 9)
Differential inputs (single−ended
measurement)
600 1150 mV
V
ILDIF
Input Low Voltage − CLK_IN
(Note 9)
Differential inputs (single−ended
measurement)
V
SS
300
300 mV
V
COM
Input Common Mode Voltage −
CLK_IN (Note 9)
Common Mode Input Voltage 300 1000 mV
V
SWING
Input Amplitude − CLK_IN (Note 9) Peak to Peak value 300 1450 mV
dv/dt
Input Slew Rate − CLK_IN (Notes 9
and 10)
Measured differentially 0.4 8 V/ns
I
IN
Input Leakage Current (Note 9)
V
IN
= V
DD
,
V
IN
= GND
−5 5
mA
d
tin
Input Duty Cycle (Note 9) Measurement from differential waveform 45 55 %
J
DIFIn
Input Jitter − Cycle to Cycle (Note 9) Differential Measurement 0 125 ps
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
9. Guaranteed by design and characterization, not tested in production.
10.Slew rate measured through ±75 mV window centered around differential zero.
Table 11. ELECTRICAL CHARACTERISTICS − DIF 0.7 V CURRENT MODE DIFFERENTIAL OUTPUTS
(V
DD
= V
DDA
= 3.3 V ±5%, T
A
= −10°C to +70°C), See Test Loads for Loading Conditions
Symbol
Parameter Conditions Min Typ Max Unit
dV/dt Slew rate (Notes 11, 12 and 13) Scope averaging on 1 4 V/ns
DdV/dt
Slew rate matching
(Notes 11, 12 and 14)
Slew rate matching, Scope averaging on 20 %
DTrf
Rise/Fall Time Matching
(Notes 11, 12 and 18)
Rise/fall matching, Scope averaging off 125 ps
V
High
Voltage High (Note 11)
Statistical measurement on single−ended
signal using oscilloscope math function.
(Scope averaging on)
660 850
mV
V
Low
Voltage Low (Note 11) −150 150
V
max
Max Voltage (Note 11)
Measurement on single ended signal using
Absolute value. (Scope averaging off)
1150
mV
V
min
Min Voltage (Note 11) −300
V
swing
Vswing (Notes 11 and 12) Scope averaging off 300 mV
V
cross_abs
Crossing Voltage (abs)
(Notes 11 and 15)
Scope averaging off 250 550 mV
DV
cross
Crossing Voltage (var)
(Notes 11 and 16)
Scope averaging off 140 mV
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
11. Guaranteed by design and characterization, not tested in production. I
REF
= V
DD
/(3xR
REF
). For R
REF
= 475 W (1%), I
REF
= 2.32 mA. I
OH
= 6 x I
REF
and V
OH
= 0.7 V @ Z
O
= 50 W (100 W differential impedance).
12.Measured from differential waveform.
13.Slew rate is measured through the Vswing voltage range centered around differential 0 V. This results in a ±150 mV window around
differential 0 V.
14.Matching applies to rising and falling edge rate of differential waveform. It is measured using a ±75 mV window centered on the average cross
point where the clock rising meets clock# falling. The median cross point is used to calculate voltage thresholds that the oscilloscope uses
to calculate the slew rate. Measurement taken using a 100 W differential impedance 5” trace PCB.
15.Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e.
Clock rising and Clock# falling).
16.The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross absolute)
allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute.
17.Measured from single−ended waveform
18.Measured with scope averaging off, using statistics function. Variation is difference between min and max.

NB3N1900KMNTWG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Clock Buffer 3.3V 1:19 HCSL FANOU
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet