AD9879
Rev. A | Page 9 of 32
Pin No. Mnemonic Description
41 SCLK SPORT Clock.
42
CS
SPORT Chip Select.
43 SDIO SPORT Data I/O.
44 SDO SPORT Data Output.
45 DGNDTX Tx Path Digital Ground.
46 DVDDTX Tx Path Digital 3.3 V Supply.
47
PWRDN
Power-Down Transmit Path.
48 REFIO TxDAC Decoupling (to AGND).
49 FSADJ DAC Output Adjust (External Resistor).
50 AGNDTX Tx Path Analog Ground.
51, 52 TX−, TX+ Tx Path Complementary Outputs.
53 AVDDTX Tx Path Analog 3.3 V Supply.
54 DGNDPLL PLL Digital Ground.
55 DVDDPLL PLL Digital 3.3 V Supply.
56 AVDDPLL PLL Analog 3.3 V Supply.
57 PLLFILT PLL Loop Filter Connection.
58 AGNDPLL PLL Analog Ground.
59 DGNDOSC Oscillator Digital Ground.
60 XTAL Crystal Oscillator Inverted Output.
61 OSCIN Oscillator Clock Input.
62 DVDDOSC Oscillator Digital 3.3 V Supply.
63 CA_CLK Serial Clock to Cable Driver.
64 CA_DATA Serial Data to Cable Driver.
65
CA_EN
Serial Enable to Cable Drive.
66 DVDD Σ-∆ Σ-∆ Digital 3.3 V Supply.
67 FLAG1 Digital Output Flag 1.
68 Σ-∆_OUT Σ-∆ DAC Output.
69 DGND Σ-∆ Σ-∆ Digital Ground.
71 REFCLK Programmable Reference Clock Output.
73 AVDDIQ 7-Bit ADCs Analog 3.3 V Supply.
74 AGNDIQ 7-Bit ADCs Analog Ground.
78, 79 I−, I+ Differential Input to I ADC.
81, 82 Q−, Q+ Differential Input to Q ADC.
83, 88, 91, 96, 99 AGND 12-Bit ADC Analog Ground.
84, 87, 92, 95 AVDD 12-Bit ADC Analog 3.3 V Supply.
85 REFB10 10-Bit ADC Decoupling Node.
86 REFT10 10-Bit ADC Decoupling Node.
89, 90 IF10−, IF10+ Differential Input to 10-Bit ADC.
93 REFB12 12-Bit ADC Decoupling Node.
94 REFT12 12-Bit ADC Decoupling Node.
97, 98 IF12−, IF12+ Differential Input to IF ADC.
100 VIDEO IN Video Clamp Input, 12-Bit ADC.
AD9879
Rev. A | Page 10 of 32
TERMINOLOGY
Aperture Delay
The aperture delay is a measure of the sample-and-hold
amplifier (SHA) performance. It specifies the time delay
between the rising edge of the sampling clock input and when
the input signal is held for conversion.
Aperture Uncertainty (Jitter)
Aperture jitter is the variation in aperture delay for successive
samples. It is manifested as noise on the input to the ADC.
Channel-to-Channel Isolation (Crosstalk)
In an ideal multichannel system, the signal in one channel does
not influence the signal level of another channel. The channel-
to-channel isolation specification is a measure of the change
that occurs to a grounded channel as a full-scale signal is
applied to another channel.
Differential Nonlinearity Error (DNL, No Missing Codes)
An ideal converter exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 10-bit resolution indicates that all 1,024
codes, respectively, must be present over all operating ranges.
Effective Number of Bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the
number of bits. Using the formula
N = (SINAD − 1.76 dB∕6.02)
it is possible to determine a measure of performance expressed
as N, the effective number of bits. Thus, the effective number of
bits for a devices sine wave inputs at a given input frequency
can be calculated directly from its measured SINAD.
Gain Error
The first code transition should occur at an analog value
1/2 LSB above full scale. The last transition should occur for an
analog value 1 1/2 LSB below the nominal full scale. Gain error
is the deviation of the actual difference between the first and
last code transitions and the ideal difference between the first
and last code transitions.
Input Referred Noise
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output code is calculated in
LSB and converted to an equivalent voltage. This results in a
noise figure that can be directly referred to the input of the MxFE.
Integral Nonlinearity Error (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale through the positive
full scale. The point used as the negative full scale occurs
1/2 LSB before the first code transition. Positive full scale is
defined as a level 1 1/2 LSB beyond the last code transition. The
deviation is measured from the middle of each code to the true
straight line.
Offset Error
First transition should occur for an analog value 1/2 LSB
above −FS. Offset error is defined as the deviation of the actual
transition from that point.
Output Compliance Range
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits can
cause either output stage saturation or break down, resulting in
nonlinear performance.
Phase Noise
Single-sideband phase noise power is specified relative to the
carrier (dBc/Hz) at a given frequency offset (1 kHz) from the
carrier. Phase noise can be measured directly in single-tone
transmit mode with a spectrum analyzer that supports noise
marker measurements. It detects the relative power between the
carrier and the offset (1 kHz) sideband noise and takes the
resolution bandwidth (RBW) into account by subtracting
10 log(RBW). It also adds a correction factor that compensates
for the implementation of the resolution bandwidth, log display,
and detector characteristic.
Pipeline Delay (Latency)
Pipeline delay is the number of clock cycles between conversion
initiation and the availability of the associated output data.
Power Supply Rejection
Power supply rejection specifies the converter’s maximum full-
scale change when the supplies are varied from nominal to
minimum and maximum specified voltages.
Signal-to-Noise and Distortion (SINAD) Ratio
SINAD is the ratio of the rms value of the measured input
signal to the rms sum of all other spectral components below
the Nyquist frequency, including harmonics but excluding dc.
The value for SINAD is expressed in decibels.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the measured input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in dB, between the rms amplitude of the
DAC output signal (or the ADC input signal) and the peak
spurious signal over the specified bandwidth (Nyquist
bandwidth, unless otherwise noted).
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal, and
is expressed as a percentage or in decibels.
AD9879
Rev. A | Page 11 of 32
THEORY OF OPERATION
To gain a general understanding of the AD9879, refer to the
block diagram of the device architecture in Figure 3. The
device consists of a transmit path, receive path, and auxiliary
functions, such as a DPLL, a Σ-Δ DAC, a serial control port,
and a cable amplifier interface.
TRANSMIT PATH
The transmit path contains an interpolation filter, a complete
quadrature digital upconverter, an inverse sinc filter, and a
12-bit current output DAC. The maximum output current of
the DAC is set by an external resistor. The Tx output PGA
provides additional transmit signal level control.
The transmit path interpolation filter provides an upsampling
factor of 16 with an output signal bandwidth as high as
5.8 MHz. Carrier frequencies up to 65 MHz with 26 bits of
frequency tuning resolution can be generated by the direct
digital synthesizer (DDS).
The transmit DAC resolution is 12 bits and can run at sampling
rates as high as 232 MSPS. Analog output scaling from 0.0 dB
to 7.5 dB in 0.5 dB steps is available to preserve SNR when
reduced output levels are required.
DATA ASSEMBLER
The AD9879 data path operates on two 12-bit words, the I and
Q components, which compose a complex symbol. The data
assembler builds the 24-bit complex symbols from four
consecutive 6-bit nibbles read over the TxIQ[5:0] bus. The
nibbles are strobed synchronous to the master clock, MCLK,
into the data assembler. A high level on TxSYNC signals the
start of a transmit symbol. The first two nibbles of the symbol
form the I component, and the second two nibbles form the Q
component. Symbol components are assumed to be in twos
complement format. The timing of the interface is fully
described in the Transmit Timing section of this data sheet.
TXIQ
TXSYNC
MCLK
REFCLK
CA_PORT
PROFILE
SPORT
RXIQ[3:0]
RXSYNC
IF[11:0]
FSADJ
XTAL
OSCIN
Σ-_OUT
FLAG1
I INPUT
Q INPUT
IF10 INPUT
IF12 INPUT
VIDEO INPUT
6
3
12
12
10
7
12
AD9879
DATA
ASSEMBLER
QUADRATURE
MODULATOR
FIR LPF
CIC LPF
COS
SIN
(f
IQCLK
)
(f
SYSCLK
)
(f
OSCIN
)
(f
MCLK
)
DAC GAIN CONTROL
PLL
OSCIN × M
DDS
MUX
MUX
CA
INTERFACE
PROFILE
SELECT
SERIAL
INTERFACE
12
4
÷4
SINC
–1
MUX
DAC
IQ
IF
CLAMP LEVEL
ADC
ADC
ADC
ADC
MUX
DAC
÷2
÷8
÷4
÷2
12
12
(f
OSCIN
)
(f
OSCIN
)
7
÷R
4
4
12
I
Q
RXPORT
TX
Σ- INPUT REGISTER
+
÷2
4
44
12
SINC
–1
BYPASS
Σ-
02773-003
Figure 3. Block Diagram

AD9879BSZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC Mixed Signal FE Set Top Box
Lifecycle:
New from this manufacturer.
Delivery:
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