AD9879
Rev. A | Page 12 of 32
INTERPOLATION FILTER
Once through the data assembler, the IQ data streams are fed
through a 4× FIR low-pass filter and a 4× cascaded integrator-
comb (CIC) low-pass filter. The combination of these two filters
results in the sample rate increasing by a factor of 16.
In addition to the sample rate increase, the half-band filters
provide the low-pass filtering characteristic necessary to
suppress the spectral images between the original sampling
frequency and the new (16× higher) sampling frequency.
DIGITAL UPCONVERTER
The digital quadrature modulator stage following the CIC filters
is used to frequency shift (upconvert) the baseband spectrum of
the incoming data stream up to the desired carrier frequency.
The carrier frequency is controlled numerically by a direct
digital synthesizer (DDS). The DDS uses the internal system
clock (f
SYSCLK
) to generate the desired carrier frequency with a
high degree of precision. The carrier is applied to the I and Q
multipliers in quadrature fashion (90° phase offset) and
summed to yield a data stream that is the modulated carrier.
The modulated carrier becomes the 12-bit sample sent to the DAC.
The receive path contains a 12-bit ADC, a 10-bit ADC, and a
dual 7-bit ADC. All internally required clocks and an output
system clock are generated by the PLL from a single crystal or
clock input.
The 12-bit and 10-bit IF ADCs can convert direct IF inputs up
to 70 MHz and run at sample rates up to 33 MSPS. A video
input with an adjustable signal clamping level along with the
10-bit ADC allow the AD9879 to process an NTSC and a QAM
channel simultaneously.
The programmable Σ-Δ DAC can be used to control external
components, such as variable gain amplifiers (VGAs) or voltage
controlled tuners. The CA_PORT provides an interface to the
AD8321/AD8323 or AD8322/AD8327 programmable gain
amplifier (PGA) cable drivers, enabling host processor control
via the MxFE SPORT.
OSCIN Clock Multiplier
The AD9879 can accept either an input clock into the OSCIN
pin or a fundamental mode XTAL across the OSCIN pin and
XTAL pins as the device’s main clock source. The internal PLL
then generates the f
SYSCLK
signal from which all other internal
signals are derived.
The DAC uses f
SYSCLK
as its sampling clock. For DDS
applications, the carrier is typically limited to about 30% of
f
SYSCLK
. For a 65 MHz carrier, the system clock required is above
216 MHz.
The OSCIN multiplier function maintains clock integrity, as
evidenced by the excellent phase noise characteristics and low
clock-related spur in the output spectrum of the AD9879’s systems.
External loop filter components consisting of a series resistor
(1.3 kΩ) and capacitor (0.01 µF) provide the compensation zero
for the OSCIN multiplier PLL loop. The overall loop
performance has been optimized for these component values.
DPLL-A CLOCK DISTRIBUTION
Figure 3 shows the clock signals used in the transmit path. The
DAC sampling clock, f
DAC
, is generated by DPLL-A. F
DAC
has a
frequency equal to L × f
OSCIN
, where f
OSCIN
is the internal signal
generated by either the crystal oscillator when a crystal is
connected between the OSCIN and XTAL pins or the clock that
is fed into the OSCIN pin, and L is the multiplier programmed
through the serial port. L can have the values of 1, 2, 3, or 8.
The transmit path expects a new half word of data at the rate of
f
CLK-A
. When the Tx multiplexer is enabled, the frequency of
Tx Port is
f
CLK−A
= 2 × f
DA
/K = 2 × L × f
OSCIN
/K (1)
where K is the interpolation factor.
The interpolation factor can be programmed to be 1, 2, or 4.
When the Tx multiplexer is disabled, the frequency of the
Tx Port is
f
CLK−A
= f
DAC
/K = L × f
OSCIN
/K (2)
Receive Section
The AD9879 includes two high speed, high performance ADCs.
The 10-bit and 12-bit direct IF ADCs deliver excellent under-
sampling performance with input frequencies as high as 70 MHz.
The sampling rate can be as high as 33 MSPS.
The ADC sampling frequency can be derived directly from the
OSCIN signal or from the on-chip OSCIN multiplier. For
highest dynamic performance, it is advisable to choose an
OSCIN frequency that can be directly used as the ADC
sampling clock. Digital IQ ADC outputs are multiplexed to one
4-bit bus, clocked by a frequency (f
MCLK
) of four times the
sampling rate. The IF ADCs use a multiplexed 12-bit interface
with an output word rate of f
MCLK
.
CLOCK AND OSCILLATOR CIRCUITRY
The internal oscillator of the AD9879 generates all sampling
clocks from a simple, low cost, parallel resonance, fundamental
frequency quartz crystal. Figure 4 shows how the quartz crystal
is connected between OSCIN (Pin 61) and XTAL (Pin 60) with
parallel resonant load capacitors as specified by the crystal
manufacturer. The internal oscillator circuitry can also be
overdriven by a TTL-level clock applied to OSCIN with XTAL
left unconnected.
f
OSCIN
= f
MCLK
× M (3)
