AD9879
Rev. A | Page 6 of 32
Parameter Temp Test Level Min Typ Max Unit
Signal-to-Noise Ratio (SNR) Full II 46.2 57.2 Bits
Total Harmonic Distortion (THD) Full II −50.1 −44.5 dB
Spurious-Free Dynamic Range (SFDR) Full II 44.9 53.4 dB
CHANNEL-TO-CHANNEL ISOLATION
Tx DAC-to-ADC Isolation (A
OUT
= 5 MHz)
Isolation Between Tx and IQ ADCs 25°C III >60 dB
Isolation Between Tx and 10-Bit ADC 25°C III >80 dB
Isolation Between Tx and 12-Bit ADC 25°C III >80 dB
ADC-to-ADC (A
IN
= –0.5 dBFS, f = 5 MHz)
Isolation Between IF10 and IF12 ADCs 25°C III >85 dB
Isolation Between Q and I Inputs 25°C III >50 dB
TIMING CHARACTERISTICS (10 pF Load)
Minimum RESET Pulse Width Low (t
RL
) N/A N/A 5 t
MCLK
cycles
Digital Output Rise/Fall Time Full II 2.8 4 ns
Tx/Rx Interface
MCLK Frequency (f
MCLK
) Full II 66 MHz
TxSYNC/TxIQ Setup Time (t
SU
) Full II 3 ns
TxSYNC/TxIQ Hold Time (t
HD
) Full II 3 ns
MCLK Rising Edge to
RxSYNC/RxIQ/IF Valid Delay (t
MD
) Full II 0 1.0 ns
REFCLK Rising or Falling Edge to
RxSYNC/RxIQ/IF Valid Delay (t
OD
) Full II T
OSC
/4 – 2.0 T
OSC
/4 + 3.0 ns
REFCLK Edge to MCLK Falling Edge (t
EE
) Full II −1.0 +1.0 ns
Serial Control Bus
Maximum SCLK Frequency (f
SCLK
) Full II 15 MHz
Minimum Clock Pulse Width High (t
PWH
) Full II 30 ns
Minimum Clock Pulse Width Low (t
PWL
) Full II 30 ns
Maximum Clock Rise/Fall Time Full II 1 ms
Minimum Data/Chip-Select Setup Time (t
DS
) Full II 25 ns
Minimum Data Hold Time (t
DH
) Full II 0 ns
Maximum Data Valid Time (t
DV
) Full II 30 ns
CMOS LOGIC INPUTS
Logic 1 Voltage 25°C II V
DRVDD
– 0.7 V
Logic 0 Voltage 25°C II 0.4 V
Logic 1 Current 25°C II 12 µA
Logic 0 Current 25°C II 12 µA
Input Capacitance 25°C II 3 pF
CMOS LOGIC OUTPUTS (1 mA Load)
Logic 1 Voltage 25°C II V
DRVDD
– 0.6 V
Logic 0 Voltage 25°C II 0.4 V
POWER SUPPLY
Supply Current, I
S
(Full Operation) 25°C II 163 184 mA
Analog Supply Current, I
AS
25°C III 95 mA
Digital Supply Current, I
DS
25°C III 68 mA
Supply Current, I
S
Standby (PWRDN Pin Active)
25°C II 119 126 mA
Full Power-Down (Register 0x02 = 0xF9) 25°C III 16 mA
Power-Down Tx Path (Register 0x02 = 0x60) 25°C III 113 mA
Power-Down Rx Path (Register 0x02 = 0x19) 25°C III 110 mA
1
IQ ADC in default mode. ADC Clock Select Register 8, Bit 3 set to 0.
