CY28416
Document #: 38-07657 Rev. *C Page 13 of 15
Test and Measurement Set-up
For Differential CPU and SRC Output Signals
The following diagram shows lumped test load configurations
for the differential Host Clock Outputs.
T
CCJ
REF Cycle to Cycle Jitter Measurement at 1.5V 1000 ps
ENABLE/DISABLE and SETUP
T
STABLE
Clock Stabilization from Power-up 1.8 ms
T
SS
Stopclock Set-up Time 10.0 ns
T
SH
Stopclock Hold Time 0 ns
AC Electrical Specifications (continued)
Parameter Description Condition Min. Max. Unit
Table 6. Maximum Lumped Capacitive Output Loads
Clock Max Load Unit
PCI Clocks 30 pF
48M Clock 20 pF
REF Clock 30 pF
CPUT
T
PCB
T
PCB
CPUC
33Ω
33Ω
49.9Ω
49.9Ω
Measurement
Point
2pF
475Ω
IR E F
Measurement
Point
2pF
Fi
g
ure 7. 0.7V Load Confi
g
uration
Figure 8. Lumped Load For Single-ended Output Signals (for AC Parameters Measurement)
0V
3.3V
2.4V
0.4V
1.5V
tDC
Tf
Tr
Output under Test
Pr ob e
Load
Cap
Ordering Information
Part Number Package Type Product Flow
Lead-free
CY28416OXC 48-pin SSOP Commercial, 0° to 70°C
CY28416OXCT 48-pin SSOP—Tape and Reel Commercial, 0
° to 70°C
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CY28416
Document #: 38-07657 Rev. *C Page 14 of 15
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document
are the trademarks of their respective holders.
Purchase of I
2
C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips
I
2
C Patent Rights to use these components in an I
2
C system, provided that the system conforms to the I
2
C Standard Specification
as defined by Philips.
Package Drawings and Dimensions
48-lead Shrunk Small Outline Package O48
51-85061-*C
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CY28416
Document #: 38-07657 Rev. *C Page 15 of 15
Document History Page
Document Title: CY28416 Next Generation FTG for Intel
®
Architecture
Document #: 38-07657 Rev. *C
REV. ECN NO. Issue Date
Orig. of
Change Description of Change
** 224420 See ECN RGL/TUJ New Data Sheet
*A 318277 See ECN RGL Changed VTTPWRGD and PCIF0 pins from PU to PD
*B 375236 See ECN RGL Changed definition of Byte 1 bit 7
Fix AC parameters table as per char data
*C 385998 See ECN RGL Removed Preliminary
Changed CPU cycle-to-cycle jitter max to 90ps
Changed SRC crossing voltage min to 220mV
Changed DOT crossing voltage min to 200mV
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CY28416OXCT

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
IC CLK GEN CPU 266MHZ 2CIRC 48SS
Lifecycle:
New from this manufacturer.
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