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DS18B20U+

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
DS18B20
7 of 22
MEMORY
The DS18B20’s memory is organized as shown in Figure 7. The memory consists of an SRAM
scratchpad with nonvolatile EEPROM storage for the high and low alarm trigger registers (T
H
and T
L
)
and configuration register. Note that if the DS18B20 alarm function is not used, the T
H
and T
L
registers
can serve as general-purpose memory. All memory commands are described in detail in the DS18B20
Function Commands section.
Byte 0 and byte 1 of the scratchpad contain the LSB and the MSB of the temperature register,
respectively. These bytes are read-only. Bytes 2 and 3 provide access to T
H
and T
L
registers. Byte 4
contains the configuration register data, which is explained in detail in the Configuration Register section.
Bytes 5, 6, and 7 are reserved for internal use by the device and cannot be overwritten.
Byte 8 of the scratchpad is read-only and contains the CRC code for bytes 0 through 7 of the scratchpad.
The DS18B20 generates this CRC using the method described in the CRC Generation section.
Data is written to bytes 2, 3, and 4 of the scratchpad using the Write Scratchpad [4Eh] command; the data
must be transmitted to the DS18B20 starting with the least significant bit of byte 2. To verify data
integrity, the scratchpad can be read (using the Read Scratchpad [BEh] command) after the data is
written. When reading the scratchpad, data is transferred over the 1-Wire bus starting with the least
significant bit of byte 0. To transfer the T
H
, T
L
and configuration data from the scratchpad to EEPROM,
the master must issue the Copy Scratchpad [48h] command.
Data in the EEPROM registers is retained when the device is powered down; at power-up the EEPROM
data is reloaded into the corresponding scratchpad locations. Data can also be reloaded from EEPROM to
the scratchpad at any time using the Recall E
2
[B8h] command. The master can issue read time slots
following the Recall E
2
command and the DS18B20 will indicate the status of the recall by transmitting 0
while the recall is in progress and 1 when the recall is done.
Figure 7. DS18B20 Memory Map
SCRATCHPAD
(POWER-UP STATE)
Byte 0 Temperature LSB (50h)
Byte 1 Temperature MSB (05h)
EEPROM
Byte 2 T
H
Register or User Byte 1* T
H
Register or User Byte 1
Byte 3 T
L
Register or User Byte 2* T
L
Register or User Byte 2
Byte 4 Configuration Register* Configuration Register
Byte 5 Reserved (FFh)
Byte 6 Reserved
Byte 7 Reserved (10h)
Byte 8 CRC*
*
Power-up state depends on value(s) stored in EEPROM.
(85°C)
DS18B20
8 of 22
CONFIGURATION REGISTER
Byte 4 of the scratchpad memory contains the configuration register, which is organized as illustrated in
Figure 8. The user can set the conversion resolution of the DS18B20 using the R0 and R1 bits in this
register as shown in Table 2. The power-up default of these bits is R0 = 1 and R1 = 1 (12-bit resolution).
Note that there is a direct tradeoff between resolution and conversion time. Bit 7 and bits 0 to 4 in the
configuration register are reserved for internal use by the device and cannot be overwritten.
Figure 8. Configuration Register
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0 R1 R0 1 1 1 1 1
Table 2. Thermometer Resolution Configuration
R1 R0
RESOLUTION
(BITS)
MAX CONVERSION
TIME
0 0 9 93.75ms (t
CONV
/8)
0 1 10 187.5ms (t
CONV
/4)
1 0 11 375ms (t
CONV
/2)
1 1 12 750ms (t
CONV
)
CRC GENERATION
CRC bytes are provided as part of the DS18B20’s 64-bit ROM code and in the 9
th
byte of the scratchpad
memory. The ROM code CRC is calculated from the first 56 bits of the ROM code and is contained in the
most significant byte of the ROM. The scratchpad CRC is calculated from the data stored in the
scratchpad, and therefore it changes when the data in the scratchpad changes. The CRCs provide the bus
master with a method of data validation when data is read from the DS18B20. To verify that data has
been read correctly, the bus master must re-calculate the CRC from the received data and then compare
this value to either the ROM code CRC (for ROM reads) or to the scratchpad CRC (for scratchpad reads).
If the calculated CRC matches the read CRC, the data has been received error free. The comparison of
CRC values and the decision to continue with an operation are determined entirely by the bus master.
There is no circuitry inside the DS18B20 that prevents a command sequence from proceeding if the
DS18B20 CRC (ROM or scratchpad) does not match the value generated by the bus master.
The equivalent polynomial function of the CRC (ROM or scratchpad) is:
CRC = X
8
+ X
5
+ X
4
+ 1
The bus master can re-calculate the CRC and compare it to the CRC values from the DS18B20 using the
polynomial generator shown in Figure 9. This circuit consists of a shift register and XOR gates, and the
shift register bits are initialized to 0. Starting with the least significant bit of the ROM code or the least
significant bit of byte 0 in the scratchpad, one bit at a time should shifted into the shift register. After
shifting in the 56th bit from the ROM or the most significant bit of byte 7 from the scratchpad, the
polynomial generator will contain the re-calculated CRC. Next, the 8-bit ROM code or scratchpad CRC
from the DS18B20 must be shifted into the circuit. At this point, if the re-calculated CRC was correct, the
shift register will contain all 0s. Additional information about the Maxim 1-Wire cyclic redundancy check
DS18B20
9 of 22
is available in Application Note 27: Understanding and Using Cyclic Redundancy Checks with Maxim
iButton Products.
Figure 9. CRC Generator
1-WIRE BUS SYSTEM
The 1-Wire bus system uses a single bus master to control one or more slave devices. The DS18B20 is
always a slave. When there is only one slave on the bus, the system is referred to as a “single-drop”
system; the system is “multidrop” if there are multiple slaves on the bus.
All data and commands are transmitted least significant bit first over the 1-Wire bus.
The following discussion of the 1-Wire bus system is broken down into three topics: hardware
configuration, transaction sequence, and 1-Wire signaling (signal types and timing).
HARDWARE CONFIGURATION
The 1-Wire bus has by definition only a single data line. Each device (master or slave) interfaces to the
data line via an open-drain or 3-state port. This allows each device to “release” the data line when the
device is not transmitting data so the bus is available for use by another device. The 1-Wire port of the
DS18B20 (the DQ pin) is open drain with an internal circuit equivalent to that shown in Figure 10.
The 1-Wire bus requires an external pullup resistor of approximately 5kΩ; thus, the idle state for the
1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus MUST be left in the idle
state if the transaction is to resume. Infinite recovery time can occur between bits so long as the 1-Wire
bus is in the inactive (high) state during the recovery period. If the bus is held low for more than 480µs,
all components on the bus will be reset.
Figure 10. Hardware Configuration
(MSB)
(LSB)
XOR
XOR
XOR
INPUT
V
PU
4.7k
5μA
TYP
Rx
Tx
DS18B20 1-Wire PORT
100
Ω
MOSFET
TX
Rx
Rx = RECEIVE
Tx = TRANSMIT
1-Wire BUS
DQ
PIN
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

DS18B20U+

Mfr. #:
Buy DS18B20U+
Manufacturer:
Maxim Integrated
Description:
Board Mount Temperature Sensors Prgmble Resolution 1-Wire Parasite Pwr
Lifecycle:
New from this manufacturer.
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