CS5165AGDWR16 Datasheet CS5165AGDW16G, CS5165AGDWR16, CS5165AGDWR16G | P1-P3

October, 2005 − Rev. 1

1 Publication Order Number:

CS5165A/D

CS5165A

5−Bit Synchronous CPU

Buck Controller

The CS5165A synchronous 5−bit NFET buck controller is

optimized to manage the power of the next generation Pentium II

processors. It’s V

t control architecture delivers the fastest transient

response (100 ns), and best overall voltage regulation in the industry

today. It’s feature rich design gives end users the maximum flexibility

to implement the best price/performance solutions for their end

products.

The CS5165A has been carefully crafted to maximize performance and

protect the processor during operation. It has a 5−bit DAC on board that

holds a ±1.0% tolerance over temperature. Its on board programmable

Soft−Start insures a control startup, and the FET nonoverlap circuitry

ensures that both FETs do not conduct simultaneously.

The on board oscillator can be programmed up to 1.0 MHz to give

the designer maximum flexibility in choosing external components

and setting systems costs.

The CS5165A protects the processor during potentially catastrophic

events like overvoltage (OVP) and short circuit. The OVP feature is

part of the V

architecture and does not require any additional

components. During short circuit, the controller pulses the MOSFETs

in a “hiccup” mode (3.0% duty cycle) until the fault is removed. With

this method, the MOSFETs do not overheat or self destruct.

The CS5165A is designed for use in both single processor desktop and

multiprocessor workstation and server applications. The CS5165A’s

current sharing capability allows the designer to build multiple parallel

and redundant power solutions for multiprocessor systems.

The CS5165A contains other control and protection features such as

Power Good, ENABLE, and adaptive voltage positioning. It is

available in a 16 lead SOIC wide body package.

Features

• V

Control Topology

• Dual N−Channel Design

• 100 ns Controller Transient Response

• Excess of 1.0 MHz Operation

• 5−Bit DAC with 1.0% Tolerance

• Power Good Output With Internal Delay

• Enable Input Provides Micropower Shutdown Mode

• 5.0 V and 12 V Operation

• Adaptive Voltage Positioning

• Remote Sense Capability

• Current Sharing Capability

• V

Monitor

• Hiccup Mode Short Circuit Protection

• Overvoltage Protection (OVP)

• Programmable Soft−Start

• 150 ns PWM Blanking

• 65 ns FET Nonoverlap Time

• 40 ns Gate Rise and Fall Times (3.3 nF Load)

• Pb−Free Packages are Available*

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

CS5165A = Device Code

A = Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

G = Pb−Free Package

PIN CONNECTIONS

SO−16WB

DW SUFFIX

CASE 751G

MARKING

DIAGRAM

ENABLE

GATE(H)C

OFF

PGNDV

ID4

GATE(L)SS

PWRGDV

ID3

LGNDV

ID2

COMPV

ID1

ID0

http://onsemi.com

CS5165A

AWLYYWWG

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

Device Package Shipping

†

ORDERING INFORMATION

CS5165AGDW16 SOIC−16 47 Units/Rail

CS5165AGDWR16 SOIC−16 1000/Tape & Ree

CS5165AGDWR16G SOIC−16

(Pb−Free)

1000/Tape & Ree

CS5165AGDW16G SOIC−16

(Pb−Free)

47 Units/Rail

CS5165A

http://onsemi.com

Figure 1. Application Diagram, 5.0 V to 2.8 V @ 14.2 A for 300 MHz Pentium II

COMP

GATE(H)

ID0

ID1

ID2

ID3

PGND

OFF

CS5165A

PCB trace

6.0 mW

12 V

330 pF

0.1 mF

LGND

1200 mF/10 V × 3

1.0 mF

Pentium II

System

ID0

ID1

ID2

ID3

1200 mF/10 V × 5

1.2 mH

5.0 V

3.3 k

1000 pF

ID4

IRL3103

GATE(L)

.1 mF

PWRGD

ENABLE

IRL3103

ENABLE

PWRGD

MAXIMUM RATINGS

Rating Value Unit

Operating Junction Temperature, T

0 to 150 °C

Lead Temperature Soldering: Reflow: (SMD styles only) (Note 1) 230 peak °C

Storage Temperature Range, T

−65 to +150 °C

ESD Susceptibility (Human Body Model) 2.0 kV

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit

values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,

damage may occur and reliability may be affected.

1. 60 second maximum above 183°C.

MAXIMUM RATINGS

Pin Name Pin Symbol V

MAX

MIN

SOURCE

SINK

IC Power Input V

16 V −0.3 V N/A 1.5 A peak, 200 mA DC

Soft−Start Capacitor SS 6.0 V −0.3 V

200 mA 10 mA

Compensation Capacitor COMP 6.0 V −0.3 V 10 mA 1.0 mA

Voltage Feedback Input V

6.0 V −0.3 V

10 mA 10 mA

Off−Time Capacitor C

OFF

6.0 V −0.3 V 1.0 mA 50 mA

Voltage ID DAC Inputs V

ID0

−V

ID4

6.0 V −0.3 V 1.0 mA

10 mA

High−Side FET Driver GATE(H) 16 V −0.3 V 1.5 A peak, 200 mA DC 1.5 A peak, 200 mA DC

Low−Side FET Driver GATE(L) 16 V −0.3 V 1.5 A peak, 200 mA DC 1.5 A peak, 200 mA DC

Enable Input ENABLE 6.0 V −0.3 V

100 mA

1.0 mA

Power Good Output PWRGD 6.0 V −0.3 V

10 mA

30 mA

Power Ground PGND 0 V 0 V 1.5 A peak, 200 mA DC N/A

Logic Ground LGND 0 V 0 V 100 mA N/A

CS5165A

http://onsemi.com

ELECTRICAL CHARACTERISTICS (0°C < T

< +70°C; 0°C < T

< +125°C; 8.0 V < V

< 14 V; 2.8 DAC Code:

ID4

= V

ID2

= V

ID1

= V

ID0

= 1; V

ID3

= 0)

;

GATE(H)

and C

GATE(L)

= 3.3 nF; C

OFF

= 330 pF; C

= 0.1 mF, unless otherwise specified.)

Characteristic Test Conditions Min Typ Max Unit

Supply Current

Operating 1.0 V < V

< V

DAC

(max on−time)

No Loads on GATE(H) and GATE(L)

− 12 20 mA

Sleep Mode ENABLE = 0 V − 300 600

Monitor

Start Threshold GATE(H) switching 3.75 3.95 4.15 V

Stop Threshold GATE(H) not switching 3.65 3.87 4.05 V

Hysteresis Start−Stop − 80 − mV

Error Amplifier

Bias Current V

= 0 V − 0.1 1.0

COMP Source Current COMP = 1.2 V to 3.6 V; V

= 2.7 V 15 30 60

COMP CLAMP Voltage

= 2.7 V, Adjust COMP voltage for Comp current = 50 mA

0.85 1.0 1.15 V

COMP Clamp Current COMP = 0 V 0.4 1.0 1.6 mA

COMP Sink Current V

COMP

= 1.2 V; V

= 3.0 V; V

> 2.5 V 180 400 800

Open Loop Gain (Note 2) 50 60 − dB

Unity Gain Bandwidth (Note 2) 0.5 2.0 − MHz

PSRR @ 1.0 kHz (Note 2) 60 85 − dB

GATE(H) and GATE(L)

High Voltage at 100 mA Measure V

− GATE − 1.2 2.0 V

Low Voltage at 100 mA Measure GATE − 1.0 1.5 V

Rise Time 1.6 V < GATE < (V

− 2.5 V) − 40 80 ns

Fall Time (V

− 2.5 V) > GATE > 1.6 V − 40 80 ns

GATE(H) to GATE(L) Delay GATE(H) < 2.0 V; GATE(L) > 2.0 V 30 65 100 ns

GATE(L) to GATE(H) Delay GATE(L) < 2.0 V; GATE(H) > 2.0 V 30 65 100 ns

GATE pulldown Resistor to PGND, (Note 2) 20 50 115

Fault Protection

SS Charge Time V

= 0 V 1.6 3.3 5.0 ms

SS Pulse Period V

= 0 V 25 100 200 ms

SS Duty Cycle (Charge Time/Period) × 100 1.0 3.3 6.0 %

SS COMP Clamp Voltage V

= 2.7 V; V

= 0 V 0.50 0.95 1.10 V

Low Comparator Increase V

till no SS pulsing and normal Off−time 0.9 1.0 1.1 V

PWM Comparator

Transient Response V

= 1.2 to 5.0 V. 500 ns after GATE(H)

(after Blanking time) to GATE(H) = (V

−1.0 V) to 1.0 V

− 130 180 ns

Minimum Pulse Width

(Blanking Time)

Drive V

FB.

1.2 to 5.0 V upon GATE(H) rising edge

(> V

− 1.0 V), measure GATE(H) pulse width

50 150 250 ns

OFF

Normal Off−Time V

= 2.7 V 1.0 1.6 2.3

Extended Off−Time V

= V

= 0 V 5.0 8.0 12.0

Time−Out Timer

Time−Out Time V

= 2.7 V, Measure GATE(H) Pulse Width 10 30 50

Fault Duty Cycle V

= 0V 30 50 70 %

Enable Input

ENABLE Threshold GATE(H) Switching 0.8 1.15 1.30 V

Shutdown delay (Note 3) ENABLE−to−GATE(H) < 2.0 V − 3.0 −

2. Guaranteed by design, not 100% tested in production.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

CS5165AGDWR16

Mfr. #:

Buy CS5165AGDWR16

Manufacturer:

ON Semiconductor

Description:

Switching Controllers 5-Bit Synchronous

Lifecycle:

New from this manufacturer.

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CS5165AGDWR16

CS5165AGDWR16

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