CS5165A
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13
Figure 24. Power Good Response to an Out of
Regulation Condition
Trace 4− V
FB
(1.0 V/div.)
Trace 2− PWRGD (2.0 V/div.)
Figure 24 shows the relationship between the regulated
output voltage V
FB
and the Power Good signal. To prevent
Power Good from interrupting the CPU unnecessarily, the
CS5165A has a built−in delay to prevent noise at the V
FB
pin
from toggling Power Good. The internal time delay is designed
to take about 75 ms for Power Good to go low and 65 ms for it
to recover. This allows the Power Good signal to be completely
insensitive to out of regulation conditions that are present for
a duration less than the built in delay (see Figure 25).
It is therefore required that the output voltage attains an out
of regulation or in regulation level for at least the built−in delay
time duration before the Power Good signal can change state.
Figure 25. Power Good is Insensitive to Out of
Regulation Conditions that are Present for a
Duration Less Than the Built In Delay
Trace 4− V
FB
(1.0 V/div.)
Trace 2− PWRGD (2.0 V/div.)
Selecting External Components
The CS5165A buck regulator can be used with a wide range
of external power components to optimize the cost and
performance of a particular design. The following information
can be used as general guidelines to assist in their selection.
NFET Power Transistors
Both logic level and standard FETs can be used. The
reference designs derive gate drive from the 12 V supply
which is generally available in most computer systems and
utilize logic level FETs. A charge pump may be easily
implemented to support 5.0 V only systems. Multiple FET’s
may be paralleled to reduce losses and improve efficiency and
thermal management.
Voltage applied to the FET gates depends on the application
circuit used. Both upper and lower gate driver outputs are
specified to drive to within 1.5 V of ground when in the low
state and to within 2.0 V of their respective bias supplies when
in the high state. In practice, the FET gates will be driven rail
to rail due to overshoot caused by the capacitive load they
present to the controller IC. For the typical application where
V
CC
= 12 V and 5.0 V is used as the source for the regulator
output current, the following gate drive is provided:
V
GS(BOTTOM)
+ 12 V
V
GS(TOP)
+ 12 V * 5.0 V + 7.0 V
(see Figure 26)
Figure 26. Gate Drive Waveforms Depicting
Rail to Rail Swing
Trace 3− GATE(H) (10 V/div.)
Trace 1− GATE(H) − 5.0 V
IN
Trace 4− GATE(L) (10 V/div.)
Trace 2− Inductor Switching Node (5.0 V/div.)
CS5165A
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14
Figure 27. Normal Operation Showing the Guaranteed
Non−Overlap Time Between the High and Low−Side
MOSFET Gate Drives, I
LOAD
= 14 A
Trace 1 = GATE(H) (5.0 V/div.)
Trace 2 = GATE(L) (5.0 V/div.)
@ 2.2 V
The CS5165A provides adaptive control of the external
NFET conduction times by guaranteeing a typical 65 ns
non−overlap between the upper and lower MOSFET gate drive
pulses. This feature eliminates the potentially catastrophic
effect of “shoot−through current”, a condition during which
both FETs conduct causing them to overheat, self−destruct, and
possibly inflict irreversible damage to the processor.
The most important aspect of FET performance is RDS
ON
,
which effects regulator efficiency and FET thermal
management requirements.
The power dissipated by the MOSFETs may be estimated as
follows:
Switching MOSFET:
Power + I
LOAD
2
RDS
ON
duty cycle
Synchronous MOSFET:
Power + I
LOAD
2
RDS
ON
(
1 * duty cycle
)
Duty Cycle =
V
OUT
) (I
LOAD
RDS
ON OF SYNCH FET
)
ƪ
V
IN
)(I
LOAD
RDS
ON OF SYNCH FET
)
* (I
LOAD
RDS
ON OF SWITCH FET
)
ƫ
Off Time Capacitor (C
OFF
)
The C
OFF
timing capacitor sets the regulator off time:
T
OFF
+ C
OFF
4848.5
The preceding equations for duty cycle can also be used
to calculate the regulator switching frequency and select the
C
OFF
timing capacitor:
C
OFF
+
Perioid
(
1 * duty cycle
)
4848.5
where:
Period +
1
switching frequency
Schottky Diode for Synchronous FET
For synchronous operation, a Schottky diode may be placed
in parallel with the synchronous FET to conduct the inductor
current upon turn off of the switching FET to improve
efficiency. The CS5165A reference circuit does not use this
device due to it’s excellent design. Instead, the body diode of
the synchronous FET is utilized to reduce cost and conducts the
inductor current. For a design operating at 200 kHz or so, the
low non−overlap time combined with Schottky forward
recovery time may make the benefits of this device not worth
the additional expense. The power dissipation in the
synchronous MOSFET due to body diode conduction can be
estimated by the following equation:
Power
+
V
BD
I
LOAD
conduction time
switching frequency
Where V
BD
= the forward drop of the MOSFET body
diode. For the CS5165A demonstration board:
Power + 1.6 V 14.2 A 100 ns 200 kHz + 0.45 W
This is only 1.1% of the 40 W being delivered to the load.
“Droop” Resistor for Adaptive Voltage Positioning
Adaptive voltage positioning is used to help keep the output
voltage within specification during load transients. To
implement adaptive voltage positioning a “Droop Resistor”
must be connected between the output inductor and output
capacitors and load. This resistor carries the full load current
and should be chosen so that both DC and AC tolerance limits
are met. An embedded PC trace resistor has the distinct
advantage of near zero cost implementation. However, this
droop resistor can vary due to three reasons: 1) the sheet
resistivity variation causes the thickness of the PCB layer to
vary. 2) the mismatch of L/W, and 3) temperature variation.
1. Sheet Resistivity for one ounce copper, the thickness
variation typically 1.15 mil to 1.35 mil. Therefore the
error due to sheet resistivity is:
1.35 * 1.15
1.25
+ 16%
2. Mismatch due to L/W. The variation in L/W is
governed by variations due to the PCB manufacturing
process that affect the geometry and the power
dissipation capability of the droop resistor. The error
due to L/W mismatch is typically 1.0%.
3. Thermal Considerations. Due to I
2
× R power losses
the surface temperature of the droop resistor will
increase causing the resistance to increase. Also, the
ambient temperature variation will contribute to the
increase of the resistance, according to the formula:
R + R
20
[1 ) a
20
(T * 20)]
where:
R
20
= resistance at 20°C
a +
0.00393
°C
T = operating temperature
R = desired droop resistor value
For temperature T = 50°C, the % R change = 12%
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15
Droop Resistor Tolerance
Tolerance due to sheet resistivity variation 16%
Tolerance due to L/W error 1.0%
Tolerance due to temperature variation 12%
Total tolerance for droop resistor 29%
In order to determine the droop resistor value the nominal
voltage drop across it at full load has to be calculated. This
voltage drop has to be such that the output voltage full load
is above the minimum DC tolerance spec.
V
DROOP(TYP)
+
[V
DAC(MIN)
* V
DC(MIN)
]
1 ) R
DROOP(TOLERANCE
)
Example: for a 300 MHz PentiumII, the DC accuracy spec
is 2.74 < V
CC(CORE)
< 2.9 V, and the AC accuracy spec is
2.67 V < V
CC(CORE)
< 2.9 3V. The CS5165A DAC output
voltage is +2.812 V < V
DAC
< +2.868 V. In order not to
exceed the DC accuracy spec, the voltage drop developed
across the resistor must be calculated as follows:
V
DROOP(TYP)
+
[V
DAC(MIN)
* V
DC
PENTIUMII(MIN)]
1 ) R
DROOP(TOLERANCE
)
+
2.812 V * 2.74 V
1.3
+ 56 mV
With the CS5165A DAC accuracy being 1.0%, the internal
error amplifiers reference voltage is trimmed so that the
output voltage will be 40 mV high at no load. With no load,
there is no DC drop across the resistor, producing an output
voltage tracking the error amplifier output voltage, including
the offset. When the full load current is delivered, a drop of
56 mV is developed across the resistor. Therefore, the
regulator output is pre−positioned at 40 mV above the
nominal output voltage before a load turn−on. The total
voltage drop due to a load step is DV−40 mV and the
deviation from the nominal output voltage is 40 mV smaller
than it would be if there was no droop resistor. Similarly at full
load the regulator output is pre−positioned at 16 mV below
the nominal voltage before a load turn−off. The total voltage
increase due to a load turn−off is DV−16 mV and the
deviation from the nominal output voltage is 16 mV smaller
than it would be if there was no droop resistor. This is because
the output capacitors are pre−charged to value that is either
40 mV above the nominal output voltage before a load
turn−on or, 16 mV below the nominal output voltage before
a load turn−off (see Figure 15).
Obviously, the larger the voltage drop across the droop
resistor ( the larger the resistance), the worse the DC and
load regulation, but the better the AC transient response.
Design Rules for Using a Droop Resistor
The basic equation for laying an embedded resistor is:
R
AR
+ ò
L
A
or R + ò
L
(W t)
where:
A = W × t = cross−sectional area
ρ = the copper resistivity (mW − mil)
L = length (mils)
W = width (mils)
t = thickness (mils)
For most PCBs the copper thickness, t, is 35 mm (1.37
mils) for one ounce copper. ρ = 717.86 mW−mil
For a Pentium II load of 14.2 A the resistance needed to
create a 56 mV drop at full load is:
Response Droop +
56 mV
I
OUT
+
56 mV
14.2 A
+ 3.9 mW
The resistivity of the copper will drift with the
temperature according to the following guidelines:
DR + 12% @ T
A
+)50°C
DR + 34% @ T
A
+)100°C
Droop Resistor Width Calculations
The droop resistor must have the ability to handle the load
current and therefore requires a minimum width which is
calculated as follows (assume one ounce copper thickness):
W +
I
LOAD
0.05
where:
W = minimum width (in mils) required for proper power
dissipation, and I
LOAD
Load Current Amps.
The Pentium
®
II maximum load current is 14.2 A.
Therefore:
W +
14.2 A
0.05
+ 284 mils + 0.7213 cm
Droop Resistor Length Calculation
L +
R
DROOP
W t
ò
+
0.0039 284 1.37
717.86
+ 2113 mil + 5.36 cm
Output Inductor
The inductor should be selected based on its inductance,
current capability, and DC resistance. Increasing the
inductor value will decrease output voltage ripple, but
degrade transient response.
Inductor Ripple Current
Ripple Current +
[(V
IN
* V
OUT
) V
OUT
]
(Switching Frequency L V
IN
)
Example: V
IN
= +5.0 V, V
OUT
= +2.8 V, I
LOAD
= 14.2 A,
L = 1.2 mH, Freq = 200 kHz
Ripple Current +
[(5.0 V * 2.8 V) 2.8 V]
[200 kHz 1.2 mH 5.0 V]
+ 5.1 A
Output Ripple Voltage
V
RIPPLE
+ Inductor Ripple Current Output Capacitor ESR
Example:
V
IN
= +5.0 V, V
OUT
= +2.8 V, I
LOAD
= 14.2 A, L = 1.2 mH,
Switching Frequency = 200 kHz
Output Ripple Voltage = 5.1 A × Output Capacitor ESR
(from manufacturers specs)
ESR of Output Capacitors to limit Output Voltage Spikes
ESR +
DV
OUT
DI
OUT

CS5165AGDWR16

Mfr. #:
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ON Semiconductor
Description:
Switching Controllers 5-Bit Synchronous
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