CS5165AGDWR16 Datasheet CS5165AGDW16G, CS5165AGDWR16, CS5165AGDWR16G | P10-P12

CS5165A

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Figure 13. Normal Operation Showing Output Inducto

Ripple Current and Output Voltage Ripple, 0.5 A Load

OUT

= +2.84 V (DAC = 10111)

Trace 1− GATE(H) (10 V/div.)

Trace 2− Inductor Switching Node (5.0 V/div.)

Trace 3− Output Inductor Ripple Current (2.0 A/div.)

Trace 4− V

OUT

ripple (20 mV/div.)

Trace 1− GATE(H) (10 V/div.)

Trace 2− Inductor Switching Node (5.0 V/div.)

Trace 3− Output Inductor Ripple Current (2.0 A/div.)

Trace 4− V

OUT

ripple (20 mV/div.)

Figure 14. Normal Operation Showing Output Inductor

Ripple Current and Output Voltage Ripple,

LOAD

= 14 A, V

OUT

= +2.84 V (DAC = 10111)

Transient Response

The CS5165A V

control loop’s 100 ns reaction time

provides unprecedented transient response to changes in

input voltage or output current. Pulse by pulse adjustment of

duty cycle is provided to quickly ramp the inductor current to

the required level. Since the inductor current cannot be

changed instantaneously, regulation is maintained by the

output capacitor(s) during the time required to slew the

inductor current.

Overall load transient response is further improved through

a feature called “Adaptive Voltage Positioning”. This

technique pre−positions the output capacitors voltage to

reduce total output voltage excursions during changes in load.

Holding tolerance to 1.0% allows the error amplifiers

reference voltage to be targeted +40 mV high without

compromising DC accuracy. A “Droop Resistor”,

implemented through a PC board trace, connects the Error

Amps feedback pin (V

) to the output capacitors and load

and carries the output current. With no load, there is no DC

drop across this resistor, producing an output voltage tracking

the Error amps, including the +40 mV offset. When the full

load current is delivered, an 80 mV drop is developed across

this resistor. This results in output voltage being offset

−40 mV low.

The result of Adaptive Voltage Positioning is that

additional margin is provided for a load transient before

reaching the output voltage specification limits. When load

current suddenly increases from its minimum level, the

output capacitor is pre−positioned +40 mV. Conversely, when

load current suddenly decreases from its maximum level, the

output capacitor is pre−positioned −40 mV (see Figures 15,

16, and 17). For best Transient Response, a combination of a

number of high frequency and bulk output capacitors are

usually used.

If the Maximum On−Time is exceeded while responding to

a sudden increase in Load current, a normal off−time occurs

to prevent saturation of the output inductor.

Figure 15. Output Voltage Transient Response to

a 14 A Load Pulse, V

OUT

= +2.84 V (DAC = 10111)

Trace 4− V

OUT

(100 mV/div.)

Trace 3− Load Current (5.0 A/10 mV/div.)

Figure 16. Output Voltage Transient Response to a

14 A Load Step, V

OUT

= +2.84 V (DAC = 10111)

Trace 1− GATE(H) (10 V/div.)

Trace 2− Inductor Switching Node (5.0 V/div.)

Trace 3− Load Current (5.0 A/div)

Trace 4− V

OUT

(100 mV/div.)

CS5165A

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Figure 17. Output Voltage Transient Response to a 14

A Load Turn−Off, V

OUT

= +2.84 V (DAC = 10111)

Trace 1− GATE(H) (10 V/div.)

Trace 2− Inductor Switching Node (5.0 V/div.)

Trace 3− Load Current (5.0 A/div)

Trace 4− V

OUT

(100 mV/div.)

PROTECTION AND MONITORING FEATURES

Short Circuit Protection

A lossless hiccup mode short circuit protection feature is

provided, requiring only the Soft−Start capacitor to implement.

If a short circuit condition occurs the V

low comparator sets

the FAULT latch. This causes the top FET to shut off,

disconnecting the regulator from it’s input voltage. The

Soft−Start capacitor is then slowly discharged by a 2.0 mA

current source until it reaches it’s lower 0.7 V threshold. The

regulator will then attempt to restart normally, operating in it’s

extended off time mode with a 50% duty cycle, while the

Soft−Start capacitor is charged with a 60 mA charge current.

If the short circuit condition persists, the regulator output

will not achieve the 1.0 V low V

comparator threshold

before the Soft−Start capacitor is charged to it’s upper 2.5 V

threshold. If this happens the cycle will repeat itself until the

short is removed. The Soft−Start charge/discharge current

ratio sets the duty cycle for the pulses (2.0 mA/60 mA = 3.3%),

while actual duty cycle is half that due to the extended off time

mode (1.65%).

This protection feature results in less stress to the regulator

components, input power supply, and PC board traces than

occurs with constant current limit protection (see Figures 18

and 19).

If the short circuit condition is removed, output voltage will

rise above the 1.0 V level, preventing the FAULT latch from

being set, allowing normal operation to resume.

Figure 18. Demonstration Board Hiccup Mode Short

Circuit Protection. Gate Pulses are Delivered While

the Soft−Start Capacitor Charges, and Cease During

Discharge

M 25.0 ms

Trace 3− Soft−Start Timing Capacitor (1.0 V/div.)

Trace 4− 5.0 V Supply Voltage (2.0 V/div.)

Trace 2− Inductor Switching Node (2.0 V/div.)

Figure 19. Demonstration Board Startup with

Regulator Output Shorted To Ground

M 50.0 ms

Trace 4− 5.0 V from PC Power Supply (2.0 V/div.)

Trace 2− Inductor Switching Node (2.0 V/div.)

Overvoltage Protection

Overvoltage protection (OVP) is provided as result of the

normal operation of the V

control topology and requires no

additional external components. The control loop responds to

an overvoltage condition within 100 ns, causing the top

MOSFET to shut off, disconnecting the regulator from it’s

input voltage. The bottom MOSFET is then activated, resulting

in a “crowbar” action to clamp the output voltage and prevent

damage to the load (see Figures 20 and 21 ). The regulator will

CS5165A

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remain in this state until the overvoltage condition ceases or the

input voltage is pulled low. The bottom FET and board trace

must be properly designed to implement the OVP function.If

a dedicated OVP output is required, it can be implemented

using the circuit in Figure 22. In this figure the OVP signal will

go high (overvoltage condition), if the output voltage (V

CORE

)

exceeds 20% of the voltage set by the particular DAC code and

provided that PWRGD is low. It is also required that the

overvoltage condition be present for at least the PWRGD delay

time for the OVP signal to be activated. The resistor values

shown in Figure 22 are for V

DAC

= +2.8 V (DAC = 10111).

The V

OVP

(overvoltage trip−point) can be set using the

following equation:

OVP

+ V

BEQ3

1 )

Figure 20. OVP Response to an Input−to−Output

Short Circuit by Immediately Providing 0% Duty

Cycle, Crow−Barring the Input Voltage to Ground

M 10.0 ms

Trace 1− Regulator Output Voltage (1.0 V/div.)

Trace 2− Inductor Switching Node 5.0 V/div.)

Trace 4− 5.0 V from PC Power Supply (5.0 V/div.)

Figure 21. OVP Response to an Input−to−Output Sho

Circuit by Pulling the Input Voltage to Ground

M 5.00 ms

Trace 1− Regulator Output Voltage (1.0 V/div.)

Trace 4− 5.0 V from PC Power Supply (2.0 V/div.)

Figure 22. Circuit To Implement A Dedicated OVP

Output Using The CS5165A

CS5165A

PWRGD

+5.0 V

10 k

2N3906

2N3904

20 k

5.0 k

+5.0 V

10 k

10 K

2N3906

56 k

15 k

CORE

Output Enable Circuit

The Enable pin (pin 8) is used to enable or disable the

regulator output voltage, and is consistent with TTL DC

specifications. It is internally pulled−up. If pulled low (below

0.8 V), the output voltage is disabled. At the same time the

Power Good and Soft−Start pins are pulled low, so that when

normal operation resumes power−up of the CS5165A goes

through the Soft−Start sequence. Upon pulling the Enable pin

low, the internal IC bias is completely shut off, resulting in

total shutdown of the Controller IC.

Power Good Circuit

The Power Good pin (pin 13) is an open−collector signal

consistent with TTL DC specifications. It is externally

pulled−up, and is pulled low (below 0.3 V) when the regulator

output voltage typically exceeds ± 8.5% of the nominal output

voltage. Maximum output voltage deviation before Power

Good is pulled low is ± 12%.

Figure 23. PWRGD Signal Becomes Logic High as

OUT

Enters −8.5% of Lower PWRGD Threshold,

OUT

= +2.84 V (DAC = 10111)

Trace 4− V

OUT

(1.0 V/div.)

Trace 2− PWRGD (2.0 V/div.)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

CS5165AGDWR16

Mfr. #:

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Switching Controllers 5-Bit Synchronous

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CS5165AGDWR16

CS5165AGDWR16

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