16
FN8119.0
March 28, 2005
CAPACITANCE (T
A
= 25°C, f = 1.0 MHz, V
CC
= 5V)
Notes: (4) This parameter is periodically sampled and not 100% tested.
EQUIVALENT A.C. LOAD CIRCUIT A.C. TEST CONDITIONS
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Notes: (1) Typical values are for T
A
= 25°C and V
CC
= 5.0V
(2) Cb = total capacitance of one bus line in pF.
Symbol Parameter Max. Units Test Conditions
C
OUT
(4)
Output Capacitance (SDA, RESET, V2FAIL)8pFV
OUT
= 0V
C
IN
(4)
Input Capacitance (SCL, WP, S0, S1) 6 pF V
IN
= 0V
V2MON
1.53k
V2FAIL
30pF
SDA
RESET
1533
30pF
5V
Input pulse levels 0.1V
CC
to 0.9V
CC
Input rise and fall times 10ns
Input and output timing levels 0.5V
CC
Output load Standard Output Load
Symbol Parameter Min. Max. Units
f
SCL
SCL Clock Frequency 0 400 kHz
t
IN
Pulse width Suppression Time at inputs 50 ns
t
AA
SCL LOW to SDA Data Out Valid 0.1 0.9 µs
t
BUF
Time the bus free before start of new transmission 1.3 µs
t
LOW
Clock LOW Time 1.3 µs
t
HIGH
Clock HIGH Time 0.6 µs
t
SU:STA
Start Condition Setup Time 0.6 µs
t
HD:STA
Start Condition Hold Time 0.6 µs
t
SU:DAT
Data In Setup Time 100 ns
t
HD:DAT
Data In Hold Time 0 µs
t
SU:STO
Stop Condition Setup Time 0.6 µs
t
DH
Data Output Hold Time 50 ns
t
R
SDA and SCL Rise Time 20 + 0.1Cb
(2)
300 ns
t
F
SDA and SCL Fall Time 20 + 0.1Cb
(2)
300 ns
t
SU:WP
WP Setup Time 0.6 µs
t
HD:WP
WP Hold Time 0 µs
Cb Capacitive load for each bus line 400 pF
X40626
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FN8119.0
March 28, 2005
TIMING DIAGRAMS
Bus Timing
WP Pin Timing
Write Cycle Timing
Nonvolatile Write Cycle Timing
Notes: (1) t
WC
is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is
the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
Symbol Parameter Min. Typ.
(1)
Max. Units
t
WC
(1)
Write Cycle Time 5 10 mS
t
SU:STO
t
DH
t
HIGH
t
SU:STA
t
HD:STA
t
HD:DAT
t
SU:DAT
SCL
SDA IN
SDA OUT
t
F
t
LOW
t
BUF
t
AA
t
R
t
HD:WP
SCL
SDA IN
WP
t
SU:WP
Clk 1 Clk 9
Slave Address Byte
START
SCL
SDA
t
WC
8th bit of Last Byte ACK
Stop
Condition
Start
Condition
X40626
18
FN8119.0
March 28, 2005
Power-Up and Power-Down Timing
RESET
Output Timing
Notes: (8) This parameter is periodically sampled and not 100% tested.
SDA vs. RESET Timing
Symbol Parameter Min. Typ. Max. Units
t
PURST
Power-up Reset Timeout 100 200 400 ms
t
RPD
(8)
V
CC
Detect to Reset/Output (Falling Edge) 500 ns
t
F
(8)
V
CC
/V2MON Fall Time 100 µs
t
R
(8)
V
CC
/V2MON Rise Time 100 µs
V
RVALID
(8)
Reset Valid V
CC
or V2FAIL Valid V2MON 1.0 V
V
TRIP
Range Voltage Range over which V
TRIP
/V
TRIP2
can be set 2.0 V
CC
V
V
CC
/V2MON
t
PURST
t
R
t
F
t
RPD
0 Volts
V
TRIP
/V
TRIP2
RESET/V2FAIL
V
RVALID
t
PURST
< t
WDO
t
RST
RESET
SDA
Start
t
WDO
t
RST
SCL
Timer Start
t
RSP
Timer
Restart
Timer Start
Start
X40626

X40626S14I-2.7

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
IC SUPERVISOR CPU DUAL 14-SOIC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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