X40626S14I-2.7 Datasheet X40626S14I-4.5A, X40626S14, X40626S14-2.7AT1 | P7-P9

FN8119.0

March 28, 2005

Table 1. Write Protect Enable Bit and WP Pin Function

Writing to the Control Register

Changing any of the nonvolatile bits of the control reg-

ister requires the following steps:

– Write a 02H to the Control Register to set the Write

Enable Latch (WEL). This is a volatile operation, so

there is no delay after the write. (Operation pro-

ceeded by a start and ended with a stop).

– Write a 06H to the Control Register to set both the

bit. This is also a volatile cycle. The zeros in the data

byte are required. (Operation proceeded by a start

and ended with a stop).

– Write a value to the Control Register that has all the

control bits set to the desired state. This can be rep-

resented as 0xys t01r in binary, where xy are the

WD bits, and rst are the BP bits. (Operation pre-

ceeded by a start and ended with a stop). Since this

is a nonvolatile write cycle it will take up to 10ms to

complete. The RWEL bit is reset by this cycle and

the sequence must be repeated to change the non-

volatile bits again. If bit 2 is set to ‘1’ in this third step

(0xys t11r) then the RWEL bit is set, but the WD1,

WD0, BP2, BP1 and BP0 bits remain unchanged.

Writing a second byte to the control register is not

allowed. Doing so aborts the write operation and

returns a NACK.

– A read operation occurring between any of the previ-

ous operations will not interrupt the register write

operation.

– The RWEL bit cannot be reset without writing to the

nonvolatile control bits in the control register, power

cycling the device or attempting a write to a write

protected block.

To illustrate, a sequence of writes to the device con-

sisting of [02H, 06H, 02H] will reset all of the nonvola-

tile bits in the Control Register to 0. A sequence of

[02H, 06H, 06H] will leave the nonvolatile bits

unchanged and the RWEL bit remains set.

SERIAL INTERFACE

Serial Interface Conventions

The device supports a bidirectional bus oriented proto-

col. The protocol defines any device that sends data

onto the bus as a transmitter, and the receiving device

as the receiver. The device controlling the transfer is

called the master and the device being controlled is

called the slave. The master always initiates data

transfers, and provides the clock for both transmit and

receive operations. Therefore, the devices in this fam-

ily operate as slaves in all applications.

Serial Clock and Data

Data states on the SDA line can change only during

SCL LOW. SDA state changes during SCL HIGH are

reserved for indicating start and stop conditions. See

Figure 5.

WP WPEN

Memory Array not

Block Protected

Memory Array

Block Protected

Block Protect

Bits WPEN Bit Protection

LOW X Writes OK Writes Blocked Writes OK Writes OK Software

HIGH 0 Writes OK Writes Blocked Writes OK Writes OK Software

HIGH 1 Writes OK Writes Blocked Writes Blocked Writes Blocked Hardware

X40626

FN8119.0

March 28, 2005

Figure 5. Valid Data Changes on the SDA Bus

Serial Start Condition

All commands are preceded by the start condition,

which is a HIGH to LOW transition of SDA when SCL

is HIGH. The device continuously monitors the SDA

and SCL lines for the start condition and will not

respond to any command until this condition has been

met. See Figure 6.

Serial Stop Condition

All communications must be terminated by a stop con-

dition, which is a LOW to HIGH transition of SDA when

SCL is HIGH. The stop condition is also used to place

the device into the Standby power mode after a read

sequence. A stop condition can only be issued after the

transmitting device has released the bus. See Figure 6.

Figure 6. Valid Start and Stop Conditions

Serial Acknowledge

Acknowledge is a software convention used to indi-

cate successful data transfer. The transmitting device,

either master or slave, will release the bus after trans-

mitting eight bits. During the ninth clock cycle, the

receiver will pull the SDA line LOW to acknowledge

that it received the eight bits of data. Refer to Figure 7.

The device will respond with an acknowledge after

recognition of a start condition and if the correct

Device Identifier and Select bits are contained in the

Slave Address Byte. If a write operation is selected,

the device will respond with an acknowledge after the

receipt of each subsequent eight bit word. The device

will acknowledge all incoming data and address bytes,

except for the Slave Address Byte when the Device

Identifier and/or Select bits are incorrect.

In the read mode, the device will transmit eight bits of

data, release the SDA line, then monitor the line for an

acknowledge. If an acknowledge is detected and no

stop condition is generated by the master, the device

will continue to transmit data. The device will terminate

further data transmissions if an acknowledge is not

detected. The master must then issue a stop condition

to return the device to Standby mode and place the

device into a known state.

SCL

SDA

Data Stable Data Change Data Stable

SCL

SDA

Start Stop

X40626

FN8119.0

March 28, 2005

Figure 7. Acknowledge Response From Receiver

Serial Write Operations

Byte Write

For a write operation, the device requires the Slave

Address Byte and a Word Address Byte. This gives the

master access to any one of the words in the array. After

receipt of the Word Address Byte, the device responds

with an acknowledge, and awaits the next eight bits of

data. After receiving the 8 bits of the Data Byte, the

device again responds with an acknowledge. The master

then terminates the transfer by generating a stop condi-

tion, at which time the device begins the internal write

cycle to the nonvolatile memory. During this internal write

cycle, the device inputs are disabled, so the device will

not respond to any requests from the master. The SDA

output is at high impedance. See Figure 8.

Figure 8. Byte Write Sequence

A write to a protected block of memory will suppress

the acknowledge bit.

Page Write

The device is capable of a page write operation. It is

initiated in the same manner as the byte write opera-

tion; but instead of terminating the write cycle after the

first data byte is transferred, the master can transmit

an unlimited number of 8-bit bytes. After the receipt of

each byte, the device will respond with an acknowl-

edge, and the address is internally incremented by

one. The page address remains constant. When the

counter reaches the end of the page, it “rolls over” and

goes back to ‘0’ on the same page. This means that

the master can write 64 bytes to the page starting at

any location on that page. If the master begins writing

at location 60, and loads 12 bytes, then the first 4

bytes are written to locations 60 through 63, and the

last 8 bytes are written to locations 0 through 7. After-

wards, the address counter would point to location 8 of

the page that was just written. If the master supplies

more than 64 bytes of data, then new data over-writes

the previous data, one byte at a time.

Data Output

from

Data Output

from Receiver

81 9

Start Acknowledge

SCL from

Master

Signals from

the Master

SDA Bus

Signals from

the Slave

Slave

Address

Byte 1

Data

1 0 1 0 0

Word Address

Byte 0

S P

Word Address

X40626

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P22

X40626S14I-2.7

Mfr. #:

Buy X40626S14I-2.7

Manufacturer:

Renesas / Intersil

Description:

IC SUPERVISOR CPU DUAL 14-SOIC

Lifecycle:

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X40626S14I-2.7

X40626S14I-2.7

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