LT1366/LT1367
LT1368/LT1369
10
1366fb
Typical perForMance characTerisTics
Capacitive Load Handling
(LT1366/LT1367)
Overshoot vs Load Current
(LT1368/LT1369)
Overshoot vs Load Current
(LT1368/LT1369)
Slew Rate vs Supply Voltage Warm-Up Drift vs Time
THD + Noise vs
Peak-to-Peak Voltage
Gain-Bandwidth and Phase
Margin vs Supply Voltage
(LT1366/LT1367) Channel Separation vs Frequency Open-Loop Gain
(The data presented here applies to the LT1366/LT1367/LT1368/LT1369 unless otherwise noted.)
SUPPLY VOLTAGE (V)
0
0
FREQUENCY (kHz)
100
150
200
250
300
350
5
10
15 20
LT1366 TPC19
25
400
450
500
50
0
12
18
24
30
36
42
48
54
60
6
30
PHASE MARGIN (DEG)
GBW
PHASE MARGIN
FREQUENCY (Hz)
–120
CHANNEL SEPARATION (dB)
–100
–90
–70
–50
10 1k 10k
LT1366 TPC20
–140
–150
100
–80
–110
–130
–60
V
S
= ±15V
V
OUT
= ±1V
P-P
R
L
= 2k
LT1368/LT1369
LT1366/LT1367
CAPACITIVE LOAD (pF)
20
OVERSHOOT (%)
40
60
80
10 1k 10k 100k
LT1366 TPC22
0
100
50
30
10
70
V
S
= 5V, 0V
A
V
= 5
A
V
= 1
A
V
= 10
LOAD CURRENT (mA)
–10
0
OVERSHOOT (%)
10
20
30
40
50
60
–5 0 5 10
LT1366 TPC23
C
L
= 0.22µF
V
S
= ±2.5V
A
V
= 1
C
L
= 0.1µF
C
L
= 0.047µF
LOAD CURRENT (mA)
–10
0
OVERSHOOT (%)
10
20
30
40
50
60
–5 0 5 10
LT1366 TPC24
C
L
= 0.22µF
V
S
= ±15V
A
V
= 1
C
L
= 0.1µF
C
L
= 0.047µF
TOTAL SUPPLY VOLTAGE (V)
0
0.10
SLEW RATE (V/µs)
0.14
0.20
8
16
20 36
LT1366 TPC25
0.12
0.18
0.16
4 12
24
28
32
A
V
= –1
TIME AFTER POWER-UP (SEC)
0
CHANGE IN OFFSET VOLTAGE (µV)
40
80
120
LT1366 TPC26
0
–40
–80
30
60
90
150
20
60
–20
–60
105
15
45
75
135
N8 PACKAGE
V
S
= ±15V
N8 PACKAGE
V
S
= ±2.5V
S8 PACKAGE
V
S
= ±15V
S8 PACKAGE
V
S
= ±2.5V
V
IN(P-P)
(V)
0.01
THD + NOISE (%)
0.1
1
10
0 2 3 4
0.001
1 5
LT1366 TPC27
f = 1kHz
R
L
= 10k
(ALL CURVES)
V
S
= ±1.5V
A
V
= 1
V
S
= ±1.5V
A
V
= –1
V
S
= ±2.5V
A
V
= 1
V
S
= ±2.5V
A
V
= –1
LT1366/LT1367
LT1368/LT1369
11
1366fb
Typical perForMance characTerisTics
(The data presented here applies to the LT1366/LT1367/LT1368/LT1369 unless otherwise noted.)
THD + Noise vs Frequency
Large-Signal Response
(LT1366/LT1367)
Small-Signal Response
(LT1366/LT1367)
FREQUENCY (kHz)
0.01
0.001
THD + NOISE (%)
0.01
0.1
1
0.1 1 10
LT1366 TPC28
V
S
= ±1.5V
V
IN
= 2V
P-P
R
L
= 10k
A
V
= 1
A
V
= –1
0V
100µs/DIV
LT1366 TPC29
V
S
= ±15V
UNITY GAIN
5V/DIV
2µs/DIV
LT1366 TPC30
V
S
= ±15V
UNITY GAIN
5mV/DIV
applicaTions inForMaTion
Rail-to-Rail Operation
The LT1366 family differs from conventional op amps in the
design of both the input and output stages. Figure 1 shows
a simplified schematic of the amplifier. The input stage
consists of two differential amplifiers, a PNP stage Q1/Q2
and an NPN stage Q3/Q4, which are active over different
portions of the input common mode range. Lateral devices
are used in both input stages, eliminating the need for
clamps across the input pins. Each input stage is trimmed
for offset voltage. A complementary output configuration
(Q23 through Q26) is employed to create an output stage
with rail-to-rail swing. The amplifier is fabricated on Linear
Q24
D7
Q23
Q25
V
V
V
V
+
V
+
V
+
V
+
V
C1
C2
Q26
D8
Q22
Q21
D6
Q17
Q16
Q18
Q15
Q19
Q20
D5D4
D7
Q11
I
1
Q10
Q14
C
C
Q13
Q9
Q8
Q7
D2
Q1 Q2
Q5
D1
Q3 Q4
Q6
D3
Q12
OUT
V
+
– 300mV
V
+
V
IN
+
IN
LT1366 FO1
Figure 1. LT1366 Simplified Schematic Diagram
LT1366/LT1367
LT1368/LT1369
12
1366fb
Technologys proprietary complementary bipolar process,
which ensures very similar DC and AC characteristics for
the output devices Q24 and Q26.
A simple comparator Q5 steers current from current source
I
1
between the two input stages. When the input common
mode voltage V
CM
is near the negative supply, Q5 is re-
verse biased, and I
1
becomes the tail current for the PNP
differential pair Q1/Q2. At the other extreme, when V
CM
is within about 1.3V from the positive supply, Q5 diverts
I
1
to the current mirror D3/Q6, which furnishes the tail
current for the NPN differential pair Q3/Q4.
The collector currents of the two input pairs are combined
in the second stage, consisting of Q7 through Q11. Most
of the voltage gain in the amplifier is contained in this
stage. Differential amplifier Q14/Q15 buffers the output
of the second stage, converting the output voltage to dif-
ferential currents. The differential currents pass through
current mirrors D4/Q17 and D5/Q16, and are converted to
differential voltages by Q18 and Q19. These voltages are
also buffered and applied to the output Darlington pairs
Q23/Q24 and Q25/Q26. Capacitors C1 and C2 form local
feedback loops around the output devices, lowering the
output impedance at high frequencies.
Input Offset Voltage
Since the amplifier has two input stages, the input offset
voltage changes depending upon which stage is active.
The input offsets are random, but bounded voltages. When
the amplifier switches between stages, offset voltages
may go up, down, or remain flat; but will not exceed the
guaranteed limits. This behavior is illustrated in three
distribution plots of input offset voltage in the Typical
Performance Characteristics section.
Overdrive Protection
Two circuits prevent the output from reversing polarity
when the input voltage exceeds the common mode range.
When the noninverting input exceeds the positive supply
by approximately 300mV, the clamp transistor Q12 (Fig-
ure
1) turns on, pulling the output of the second stage
low, which forces the output high. For inputs below the
negative supply, diodes D1 and D2 turn on, overcoming
the saturation of the input pair Q1/Q2.
When overdriven, the amplifier draws input current that
exceeds the normal input bias current. Figures 2 and 3
show some typical overdrive currents as a function of
input voltage. The input current must be less than 1mA of
positive overdrive or less than 7mA of negative overdrive,
for the phase reversal protection to work properly. When
the amplifier is severely overdriven, an external resistor
should be used to limit the overdrive current. In addition
to overdrive protection, the amplifier is protected against
ESD strokes up to 4kV on all pins.
applicaTions inForMaTion
COMMON MODE VOLTAGE RELATIVE TO
POSITIVE SUPPLY (mV)
–500
0
INPUT BIAS CURRENT (nA)
20
40
60
80
–300 –100 V
S
LT1366 F02
100
100
110
90
70
50
30
10
300 500
T = –55°C
T = 25°C
T = 85°C
T = 70°C
MEASURED AS A
FOLLOWER
+
Figure 2. Input Bias Current vs Common Mode Voltage
COMMON MODE VOLTAGE RELATIVE TO
NEGATIVE SUPPLY (mV)
–800
–110
INPUT BIAS CURRENT (nA)
–90
–70
–50
–30
–600 –400
LT1366 F03
–200
–10
0
–20
–40
–60
–80
–100
V
S
200
T = –55°C T = 25°C
T = 85°C
+
T = 70°C
MEASURED AS A FOLLOWER
Figure 3. Input Bias Current vs Common Mode Voltage

LT1367CS#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Operational Amplifiers - Op Amps 4x Prec R2R In & Out Op Amps
Lifecycle:
New from this manufacturer.
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