LT1366/LT1367
LT1368/LT1369
14
1366fb
Precision Low Dropout Regulator
Microprocessors and complex digital circuits frequently
specify tight control of power supply characteristics. The
circuit shown in Figure 6 provides a precise 3.6V, 1A output
from a minimum 3.8V input voltage. The circuit’s nominal
operating voltage is 4.75V ±5%. The voltage reference
and resistor ratios determine output voltage accuracy,
while the LT1366’s high gain enforces 0.2% line and load
regulation. Quiescent current is about 1mA and does not
change appreciably with supply or load. All components
are available in surface mount packages.
The regulator’s main loop consists of A1 and a logic-level
FET, Q1. The output is fed back to the op amp’s positive
input because of the phase inversion through Q1. The
regulator’s frequency response is limited by Q1’s roll-off
and the phase lead introduced by the output capacitor’s
effective series resistance (ESR). Two pole-zero networks
compensate for these effects. The pole formed with R5
and C2 rolls off the gain set with the feedback network,
while the pole formed with R7 and C3 rolls off A1’s gain
directly, which is the dominant influence on settling time.
The zeros formed with R6 and C2, and R8 and C3 provide
phase boost near the unity-gain crossover, which increases
Typical applicaTions
the regulator’s phase margin. Although not directly part
of the compensation, R9 decouples the op amp’s output
from Q1’s large gate capacitance.
A second loop provides a foldback current limit. A2 com-
pares the sense voltage across R1 with 50mV referenced
to the positive rail. When the sense voltage exceeds the
reference, A2’s output drives Q1’s gate positive via A1.
In current limit, the output voltage collapses and the
current limit LED (D1) turns on causing about 30mV to
drop across R3. A2 regulates Q1’s drain current so that
the deficit between the 50mV reference and the voltage
across R3 is made up across the sense resistor. The
reduced sense voltage is 20mV, which sets the current
limit to about 400mA. As the supply voltage increases, the
voltage across R3 increases, and the current limit folds
back to a lower level. The current limit loop deactivates
when the load current drops below the regulated output
current. When the supply turns on rapidly, C1 bypasses
the fold back circuit allowing the regulator to start-up into
a heavy load.
Q1 does not require a heat sink. When mounted on a type
FR4 PC board, Q1 has a thermal resistance of 50°C/W. At
1.4W worst-case dissipation, Q1 can operate up to 80°C.
C5
47µF
C4
1µF
C1
10µF
C3
6.8nF
R2
2k
R7
13k
R8
2k
R1
0.05Ω
R3
20Ω
R9
100Ω
V
IN
= 4.75V ±5%
R4
10k
D1
1.5k
Q1
Si9433DY
10k
38.5k*
D2
1N4148
5k
LT1004-1.2
R5*
20k
C2
6.8nF
R6
6.2k
R
MIN
**
1k
C
LOAD
10µF
V
OUT
3.6V
1A
Q2
2N3904
23.2k
4.75V TO 3.6V LDO AT 1A
1% METAL FILM
SET R
MIN
BASED ON LOAD CHARACTERISTICS
*
**
–
+
–
+
+
50mV
–
A1
1/2 LT1366
A2
1/2 LT1366
0.1µF
LT1366 F06
+
+
+
Figure 6. Precision 3.6V, 1A Low Dropout Regulator
